2009 IEEE Computer Society Annual Symposium on VLSI最新文献

Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS 可扩展通信核心概述:65nm CMOS可重构无线基带

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.15

A. Chun, Kyle McCanta, E. Sandoval, Kapil Gulati

引用次数: 9

Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs 基于大单元设计的串扰噪声最小化的平面驱动高电平合成

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.59

Hariharan Sankaran, S. Katkoori

{"title":"Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs","authors":"Hariharan Sankaran, S. Katkoori","doi":"10.1109/ISVLSI.2009.59","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.59","url":null,"abstract":"In DSM regime, due to higher interconnect densities, the coupling noise between adjacent signals is aggravated and can lead to many timing violations. In traditional high-level synthesis (HLS), due to lack detailed physical details, it is difficult to accurately estimate crosstalk. Crosstalk minimization is typically done during routing, which makes it computationally expensive to be used within an iterative design flow. In this paper, we propose a floorplan driven highlevel synthesis framework for minimizing crosstalk in a bus-based architecture. The proposed framework employs a Simulated Annealing engine to simultaneously explore HLS (scheduling, allocation, and binding) and floorplan (module swap, module move, and module rotate) subspaces. The effect of a high-level decision is evaluated by updating the floorplan and identifying crosstalk prone buses (i.e., those buses exceeding Lcrit). The primary goal is to minimize the number of crosstalk violations with minimum area and latency overheads. We have validated the approach by synthesizing netlists down to layout-level using Cadence-SOC encounter followed by detailed crosstalk noise analysis using Cadence Celtic. Experimental results for three DSP benchmarks (DCT, EWF, and FFT) demonstrate that the proposed approach can reduce crosstalk violations by as much as 96% (in 180 nm technology node) with an average reduction of 75% over the designs synthesized with traditional sequential flow.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123548996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Efficient Rerouting Algorithms for Congestion Mitigation 缓解拥塞的有效重路由算法

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.38

M. Chaudhry, Z. Asad, A. Sprintson, J. Hu

引用次数: 3

An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform 基于离散小波变换的高效多媒体加密认证硬件架构

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.26

A. Pande, Joseph Zambreno

引用次数: 9

Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs 基于双vdd平台fpga的寿命可靠性感知设计流程技术

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.42

P. Mangalagiri, N. Vijaykrishnan

引用次数: 3

Scheduling for an Embedded Architecture with a Flexible Datapath 具有灵活数据路径的嵌入式架构调度

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.6

Thomas Schilling, Magnus Själander, P. Larsson-Edefors

{"title":"Scheduling for an Embedded Architecture with a Flexible Datapath","authors":"Thomas Schilling, Magnus Själander, P. Larsson-Edefors","doi":"10.1109/ISVLSI.2009.6","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.6","url":null,"abstract":"Embedded systems put stringent demands on post-fabrication flexibility as well as computing performance efficiency. The FlexSoC scheme approaches the implementation of embedded systems from a general-purpose processor point of view: The FlexCore processor has a datapath whose configuration is under instruction control; in its minimal configuration, the processor represents a simple 5-stage pipeline. However, thanks to a flexible processor interconnect, the FlexCore datapath configuration can be changed at run-time to boost performance for the currently executed code. The consequence of this flexibility is that pipelining is not hard-coded into the datapath, but all instruction scheduling needs to be done by software at compile time. We present a scheduling technique for the FlexCore processor allowing for efficient use of datapath resources over a flexible interconnect. The flexible interconnect indeed offers plenty of opportunities for parallel operations, but it also makes the analysis of instruction dependencies difficult. Thus, we propose to use a SAT-solver to enable the scheduler to efficiently check constraints on computing and communication resources. In an evaluation on four different benchmarks, our scheduler is shown to produce schedules that are as efficient as fine-tuned, manual schedules.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129727708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Variation Aware Routing for Three-Dimensional FPGAs 三维fpga的变化感知路由

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.44

Chen Dong, S. Chilstedt, Deming Chen

引用次数: 8

Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC) 纳米级芯片上密码系统(CoC)的泄漏功率与侧信道安全性

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.46

Amir Khatib Zadeh, C. Gebotys

引用次数: 2

NoC Power Optimization Using a Reconfigurable Router 使用可重构路由器的NoC电源优化

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.7

C. Concatto, D. Matos, L. Carro, F. Kastensmidt, A. Susin, M. Kreutz

引用次数: 22

Dual-Sum Single-Carry Self-Timed Adder Designs 双和单进位自计时加法器设计

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.13

P. Balasubramanian, D. Edwards

引用次数: 11