Dual-Sum Single-Carry Self-Timed Adder Designs

Abstract

This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, constructed using commercially available synchronous library resources (standard cells) and validated using synchronous tools. Specifically, the proposed adder modules qualify as either quasi-delay-insensitive or speed-independent and satisfy Seitz’s weak-indication timing constraints. The delay-insensitive version of the ripple carry adder topology has been used to analyze the designs. The indication (completion) is either made implicit in the topology (local indication) or considerably isolated from the actual data path (a new variant of global indication). The proposed adders are found to exhibit improved power and performance parameters, whilst being competitive in terms of area, in comparison with those pertaining to other self-timed logic realizations