2009 IEEE Computer Society Annual Symposium on VLSI最新文献_第5页

All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex 基于互斥锁的90nm全数字占空比校正电路

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.41

S. Ramasahayam, M. Srinivas

引用次数: 9

Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems 软实时嵌入式系统中二级缓存的动态重构

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.22

Weixun Wang, P. Mishra

引用次数: 32

Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip 利用片上网络诱导多核系统的热感知

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.25

David Atienza Alonso, E. Martinez

引用次数: 13

High Speed Parallel Architecture for Cyclic Convolution Based on FNT 基于FNT的循环卷积高速并行结构

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.10

Jian Zhang, Shuguo Li

引用次数: 6

Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs 异步设计模块化验证中基于同步的抽象细化

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.16

Hao Zheng, Haiqiong Yao, T. Yoneda

引用次数: 2

On-the-Fly Evaluation of FPGA-Based True Random Number Generator 基于fpga的真随机数发生器的动态评价

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.33

R. Santoro, O. Sentieys, S. Roy

引用次数: 32

Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering 采用预滤波技术提高片上数字热传感器的灵敏度

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.31

Zhimin Chen, Raghunandan Nagesh, A. Reddy, P. Schaumont

{"title":"Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering","authors":"Zhimin Chen, Raghunandan Nagesh, A. Reddy, P. Schaumont","doi":"10.1109/ISVLSI.2009.31","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.31","url":null,"abstract":"Thermal monitoring has been broadly used to protect high-end integrated circuits from over-heating and to identify hot-spots in complex circuits. In this paper, we present a method to increase the sensitivity of an on-chip digital thermal sensor. In contrast to the existing mechanisms that characterize the overall temperature profile on a die, our solution is able to detect the submerged thermal variation caused by specific predefined events (SPE), under the precondition that the SPE’s dominant frequency does not overlap with those of other thermal events. This is made possible by pre-filtering of the temperature value. A demonstrator is implemented in an ordinary FPGA, in which the SPE is a person’s finger touching on the FPGA package. We successfully show that our design can do a correct and reliable detection of the finger touching event while ignoring other larger variations caused by other reasons. Because the finger touching event has no other special characteristics except for its unique frequency, we conclude that our solution is also applicable to other SPEs, especially low-frequency ones. In general, our method is sensitive, reliable and also flexible.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mapping Data and Code into Scratchpads from Relocatable Binaries 将数据和代码从可重新定位的二进制文件映射到scratchpad

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.28

Alexandre K. I. Mendonça, D. Volpato, José Luís Almada Güntzel, L. Santos

{"title":"Mapping Data and Code into Scratchpads from Relocatable Binaries","authors":"Alexandre K. I. Mendonça, D. Volpato, José Luís Almada Güntzel, L. Santos","doi":"10.1109/ISVLSI.2009.28","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.28","url":null,"abstract":"Scratchpad memories (SPMs) are promising for energy-efficient embedded systems. Most optimizing techniques for mapping data and code elements to SPMs assume the availability of source code. However, embedded software development has to cope with legacy code, third-party software, and IP-protected applications for which only the binaries are available. The few techniques that directly handle binaries operate on executable files and are limited to either code or data. This work proposes a new technique that addresses both data and code allocation into SPMs. Since it operates directly on binaries, the technique allows library elements to be eligible for SPM mapping. It consists of three main engines: a profiler, a mapper and a patcher. The patcher was designed to operate upon relocatable object binaries so as to overcome the inefficiency of bookkeeping SPM relocations on executable binaries. As compared to code-only SPM mapping, an average energy saving of 15% was obtained for a varied set of benchmark programs and memory configurations. Savings around 47% were reached for the two programs with higher static data content. The average patching time was 0.23s on a quad-core workstation.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123484776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect 基于主动端接芯片到芯片互连的高速低电流双二进制信号

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.9

V. Pasupureddi, P. Mandal, Sunil Sachdev

{"title":"High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect","authors":"V. Pasupureddi, P. Mandal, Sunil Sachdev","doi":"10.1109/ISVLSI.2009.9","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.9","url":null,"abstract":"In this work we propose high-speed low-current duobinary signaling scheme over an active terminated chip-to-chip interconnect. The active termination scheme eliminates the need of any dedicated passive terminator both at the transmitter and receiver, avoiding signal reflection. Elimination of the passive terminator helps to reduce the transmitted signal level without effecting signal detect-ability of the receiver and also removes the thermal noise of the terminator. To implement bandwidth efficient duobinary signaling, we present a current-mode high-speed precoder operating at 10-Gb/s. A low-current active terminated driver based on modified Cherry-Hooper topology is proposed. At the receive-end, we propose an active terminated current-mode receiver(Rx) with regulated gate cascode (RGC) based transimpedance amplifier(TIA). Folded active inductor peaking is used to enhance the bandwidth of this TIA. We also propose lowpower broadband equalizer topology for channel equalization. The duobinary transmitter and receiver circuits are implemented in 1.8-V, 0.18-μm Digital CMOS technology with an f_T of 27-GHz. The designed high speed duobinary Tx/Rx circuits work up-to 8-Gb/s speed while transmitting the data over FR4 PCB trace of length 29.5-inch and for the targeted bit-error-rate(BER) of 10^−12. The power consumed in the transmitter and receiver circuits is 42.9-mW at 8-Gb/s","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126483913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC 一个8位1.8 V 500 MSPS CMOS分段电流转向DAC

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.12

Santanu Sarkar, S. Banerjee

引用次数: 28