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Change impact analysis for hardware designs from natural language to system level 从自然语言到系统层次的硬件设计变更影响分析
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880369
Martin Ring, Jannis Stoppe, Christoph Lüth, R. Drechsler
{"title":"Change impact analysis for hardware designs from natural language to system level","authors":"Martin Ring, Jannis Stoppe, Christoph Lüth, R. Drechsler","doi":"10.1109/FDL.2016.7880369","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880369","url":null,"abstract":"Design processes are increasingly moving to more abstract description levels; no single formalism can handle the complexities of modern designs. However, keeping designs consistent across different abstraction levels, in particular in the presence of changes, has up to now been an arduous manual task. This paper presents a framework which provides a uniform, interconnected representation of the descriptions across the abstraction levels, starting from natural language requirement specifications over SysML design specifications down to executable SystemC models, allowing to track changes on all levels of abstraction, and ensuring consistency throughout the development process. The framework has been implemented in a tool, CHIMPANC, to show its viability. It assists the developer by highlighting inconsistencies and proof obligations across various descriptions levels in order to simplify the development process.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126512253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fault-effect analysis on system-level hardware modeling using virtual prototypes 基于虚拟样机的系统级硬件建模的故障效应分析
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880368
Bogdan-Andrei Tabacaru, M. Chaari, W. Ecker, T. Kruse, C. Novello
{"title":"Fault-effect analysis on system-level hardware modeling using virtual prototypes","authors":"Bogdan-Andrei Tabacaru, M. Chaari, W. Ecker, T. Kruse, C. Novello","doi":"10.1109/FDL.2016.7880368","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880368","url":null,"abstract":"Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per- formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single- bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129473518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation 用BIP对遗留代码建模:如何减少正式描述和实时实现之间的差距
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880385
Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau, M. Jan, Hela Guesmi
{"title":"Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation","authors":"Briag Le Nabec, Belgacem Ben Hedia, Jean-Philippe Babau, M. Jan, Hela Guesmi","doi":"10.1109/FDL.2016.7880385","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880385","url":null,"abstract":"To reduce the gap between high-level functional descriptions and real-time multitasking implementation, this paper proposes a set of modeling and code generation principles. Modeling principles are based on integration of a specific BIP concurrent component. This component follows a specific behavioral pattern based on periodic activation of data consumption, data processing and data production. It acts as a periodic task at execution stage. The pattern proposes two variants for eventtriggered and time-triggered platforms. The approach has been tested on three case studies, showing the interest of formalization for behavioral verification. The proposed pattern allows real-time validation and offers classical advantages of high-level modeling.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134551963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study 形式故障定位在自动RTL-to-TLM故障对应分析中的应用，实现快速准确的基于虚拟机的误差效应仿真
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880375
V. Herdt, H. M. Le, Daniel Große, R. Drechsler
{"title":"On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study","authors":"V. Herdt, H. M. Le, Daniel Große, R. Drechsler","doi":"10.1109/FDL.2016.7880375","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880375","url":null,"abstract":"Electronic systems integrate an increasingly large number of components on a single chip. This leads to increased risk of faults, e.g. due to radiation, aging etc. Such a fault can lead to an observable error and failure of the system. Therefore, an error effect simulation is important to ensure the robustness and safety of these systems. Error effect simulation with Virtual Prototypes (VPs) is much faster than with RTL designs due to less modeling details at TLM. However, for the same reason, the simulation results with VP might be significantly less accurate compared to RTL. To improve the quality of a TLM error effect simulation, a fault correspondence analysis between both abstraction levels is required. This paper presents a case study on applying fault localization methods based on symbolic simulation to identify corresponding TLM errors for transient bit flips at RTL. First results for the interrupt controller of the SoCRocket VP, which is being used by the European Space Agency, demonstrate the applicability of our approach.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124181469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking 基于概率模型检验的安全关键系统高效概率故障树分析
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880373
Marwan Ammar, Ghaith Bany Hamad, O. Mohamed, Y. Savaria
{"title":"Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking","authors":"Marwan Ammar, Ghaith Bany Hamad, O. Mohamed, Y. Savaria","doi":"10.1109/FDL.2016.7880373","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880373","url":null,"abstract":"The cost and complexity involved in the development of critical systems encourage the use of reliability assessment techniques as early in the design cycle as possible. Existing techniques often lack the capacity to perform a comprehensive and exhaustive analysis on complex redundant architectures, leading to less than optimal risk evaluation. This paper addresses these weaknesses by 1) proposing a new probabilistic modeling of Fault Tree gates and their composition as Markov Decision Processes; 2) developing a new formal-based technique to perform an in-depth verification of the system’s reliability. This technique makes use of the expressiveness of fault trees and the power of probabilistic model checking in order to investigate the best Triple Modular Redundancy partitioning and configuration of a system. The presented approach greatly improves the overall scalability with respect to other techniques, while also improving the accuracy of the results. For example, we can provide probabilistic failure rates for a chain of 100 redundant components in little over one second.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133992173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Feature based state space coverage of analog circuits 基于特征的模拟电路状态空间覆盖
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880388
Andreas Furtig, S. Steinhorst, L. Hedrich
{"title":"Feature based state space coverage of analog circuits","authors":"Andreas Furtig, S. Steinhorst, L. Hedrich","doi":"10.1109/FDL.2016.7880388","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880388","url":null,"abstract":"This paper proposes a systematic and fast analog coverage-driven verification methodology which could increase the confidence in verification of today’s analog blocks. We define an appropriate coverage metric to score simulations and then minimize the simulation effort for achieving full state space coverage with an algorithm generating appropriate input stimuli. Our proposed method uses characteristic properties of a discretized representation of the state space such as the spatial distribution of eigenvalues, guiding the generation of short and purposeful stimuli. The experimental results show a significant speed-up with similar accuracy compared to the state-of-the-art.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124820669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Cascading metamodels from different sources for performance analysis of a power module 来自不同来源的级联元模型，用于电源模块的性能分析
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880386
Christine Forster, S. Buschhorn, M. Rafaila, L. Maurer, G. Pelz
{"title":"Cascading metamodels from different sources for performance analysis of a power module","authors":"Christine Forster, S. Buschhorn, M. Rafaila, L. Maurer, G. Pelz","doi":"10.1109/FDL.2016.7880386","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880386","url":null,"abstract":"During the development process of a semiconductorbased product several types of results are generated, often in large volumes, e.g. simulation or test measurements. These have to be processed and can then be used as a reusable knowledge base for further experiments/developments. Hence, to manage such knowledge from various data sources, it is not sufficient to use classical data analysis methods. A compressed representation of this information, showing only what is important with respect to the systems performance, is desirable. We develop a method to support the combination of information from different sources and to represent it. The concept is based on cascading metamodels: The outputs of metamodels become inputs to subsequent metamodels, and mathematical composition operators can be generated for this concatenating procedure. This method is applied to a power module in order to perform sensitivity analysis on the combined metamodel.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124935397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flexible runtime verification based on logical clock constraints 基于逻辑时钟约束的灵活运行时验证
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880366
Daian Yue, V. Joloboff, F. Mallet
{"title":"Flexible runtime verification based on logical clock constraints","authors":"Daian Yue, V. Joloboff, F. Mallet","doi":"10.1109/FDL.2016.7880366","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880366","url":null,"abstract":"We present in this paper a method and tool for the verification of causal and temporal properties of embedded systems, by analyzing the trace streams resulting from virtual prototypes that combines simulated hardware and embedded software. The proposed method makes it possible to analyze different kinds of properties without rebuilding the simulation models. Logical clocks are used to identify relevant points to put observation probes and thus also reducing the trace streams size. We propose a property specification language, called PSML, and based on behavioral patterns that does not require knowledge of temporal logics. From a given PSML specification, simulation is instrumented to generate a trace and the code is dynamically loaded by the simulator. The resulting trace stream is analyzed by parallel automata generated from the specification. The experiments, developed over the SimSoC virtual prototyping framework, show flexibility, possibility of using multi-core platforms to parallelize simulation and verification, providing fast results.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Heterogeneous computing with accelerators: an overview with examples 使用加速器的异构计算:示例概述
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880387
A. Varbanescu, Jie Shen
{"title":"Heterogeneous computing with accelerators: an overview with examples","authors":"A. Varbanescu, Jie Shen","doi":"10.1109/FDL.2016.7880387","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880387","url":null,"abstract":"Accelerator-based platforms are heterogeneous in nature, yet most applications avoid heterogeneity, and focus on acceleration alone. Platform-level heterogeneity can bring significant performance improvement, as it essentially means using additional resources for the same computation. But is the performance gained using these additional resources worth the effort to program and deploy heterogeneous applications? In this work, we present a taxonomy of the existing programming models and tools available for heterogeneous computing with accelerators, and give examples of systems fitting different classes. We further provide guidelines for efficiently navigating this landscape in the search for a suitable tool for designing and deploying a new application.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems 异构系统可扩展功率建模的选择抽象和随机方法
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880376
A. Rafiev, Fei Xia, A. Iliasov, Rem Gensh, Ali Aalsaud, A. Romanovsky, A. Yakovlev
{"title":"Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems","authors":"A. Rafiev, Fei Xia, A. Iliasov, Rem Gensh, Ali Aalsaud, A. Romanovsky, A. Yakovlev","doi":"10.1109/FDL.2016.7880376","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880376","url":null,"abstract":"With the increase of system complexity in both platforms and applications, power modelling of heterogeneous systems is facing grand challenges from the model scalability issue. To address these challenges, this paper studies two systematic methods: selective abstraction and stochastic techniques. The concept of selective abstraction via black-boxing is realised using hierarchical modelling and cross-layer cuts, respecting the concepts of boxability and error contamination. The stochastic aspect is formally underpinned by Stochastic Activity Networks (SANs). The proposed method is validated with experimental results from Odroid XU3 heterogeneous 8-core platform and is demonstrated to maintain high accuracy while improving scalability.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128540712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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