Fault-effect analysis on system-level hardware modeling using virtual prototypes

Abstract

Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per- formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single- bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.