{"title":"Using event-B and Modelica to evaluate thermal management strategies in many core systems","authors":"C. Snook, T. Kazmierski","doi":"10.1109/FDL.2016.7880380","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880380","url":null,"abstract":"Dynamic thermal management is an increasingly critical and complex part of the run-time management of manycore systems. Methods of controlling temperature include thread migration, dynamic voltage and frequency scaling and power gating using various strategies and combinations of each. In the PRiME project we are developing run-time management systems to sustain the scaling of many-core systems. As part of this development we are investigating the relative benefits of different thermal management strategies by co-simulating a Modellica model of the characteristics of a many-core device with a discrete Event-B model of the run-time manager. The results enable us to efficiently design more elaborate experiments on real hardware platforms in order to validate the run time management.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"28 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic generation of self-adaptive transactors from PSL assertions","authors":"Florenc Demrozi, G. Pravadelli, F. Stefanni","doi":"10.1109/FDL.2016.7880370","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880370","url":null,"abstract":"This paper presents an approach to automatically generate transactors that implement TLM protocols for RTL IPs, such that the RTL IPs can be abstracted towards corresponding TLM models and easily integrated inside a TLM virtual prototype. The obtained transactor is self-adaptive, since it allows plugging the target IP in the virtual prototype independently from the protocol implemented by the corresponding TLM initiator. The transactor is automatically created from the set of PSL assertions that describe the temporal behaviour of the communication protocol of the original RTL IP.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Barner, Alexander Diewald, Fernando Eizaguirre, A. Vasilevskiy, Franck Chauvel
{"title":"Building product-lines of mixed-criticality systems","authors":"S. Barner, Alexander Diewald, Fernando Eizaguirre, A. Vasilevskiy, Franck Chauvel","doi":"10.1109/FDL.2016.7880378","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880378","url":null,"abstract":"Mixed-Criticality Systems (MCS) reconcile safetycritical requirements with multi-core architectures, by offering spatial and temporal isolation while preserving other extrafunctional properties such as optimised energy consumption or minimised latencies. MCS designers struggle to manually balance the offered functionalities with pertinent implementation choices in order to ensure that the system eventually meets all constraints. Existing attempts to further automate this process focus on specific concerns, and fail to account for variation in system functionalities. Our contribution is to integrate product-lines that capture functional variations with evolutionary optimisation to explore possible implementations and their impact on extrafunctional properties. Our solution is a model-driven process (and a tool prototype) to automatically select functionally different products that balance well the various concerns of interest. We illustrate how this process applies to the construction of wind turbines. Moving toward product-lines eventually contributes to reduce high development costs and the long time to market associated with MCS.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116349284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ramakrishna Nittala, Francesco Barchi, Gianvito Urgese, A. Acquaviva
{"title":"Toolchain integration of runtime variability and aging awareness in multicore platforms","authors":"Ramakrishna Nittala, Francesco Barchi, Gianvito Urgese, A. Acquaviva","doi":"10.1109/FDL.2016.7880384","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880384","url":null,"abstract":"The impact of process variations and wear-out mechanisms in current and next generation technology nodes is becoming relevant and cannot be compensated at the device or architectural level. Intra-die process variations raising at the core level and platform level makes parallel multicore platforms intrinsically heterogeneous, because the various cores are clocked at different operational frequencies. Power consumption becomes heterogeneous too, both considering dynamic and leakage consumption. Wear-out processes add further uncertainty over time. In this context, to fully exploit the computational capability of the platform parallelism, variability and wear-out aware task allocation strategies must be developed. In this work, we discuss techniques to perform task allocation and we show how they can be integrated in a software toolchain. We report results of the implementation of variability and wear-out awareness in stateof- art multicore platforms.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":" 68","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bram van der Sanden, J. Bastos, J. Voeten, M. Geilen, M. Reniers, T. Basten, Johan Jacobs, R. Schiffelers
{"title":"Compositional specification of functionality and timing of manufacturing systems","authors":"Bram van der Sanden, J. Bastos, J. Voeten, M. Geilen, M. Reniers, T. Basten, Johan Jacobs, R. Schiffelers","doi":"10.1109/FDL.2016.7880372","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880372","url":null,"abstract":"This paper introduces a formal modeling approach for compositional specification of both functionality and timing of manufacturing systems. Functionality aspects can be considered orthogonally to timing aspects. The functional aspects are specified using two abstraction levels; high-level activities and lower level actions. Design of a functionally correct controller is possible by looking only at the activity level, abstracting from the different execution orders of actions and their timing. As a result, controller design can be performed on a much smaller state space compared to an explicit model where timing and actions are present. The performance of the controller can be analyzed and optimized by taking into account the timing characteristics. Since formal semantics are given in terms of a (max, +) state space, various existing performance analysis techniques can be used. We illustrate the approach, including performance analysis, on an example manufacturing system.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123551126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A modular design space exploration framework for multiprocessor real-time systems","authors":"N. Khalilzad, Kathrin Rosvall, I. Sander","doi":"10.1109/FDL.2016.7880377","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880377","url":null,"abstract":"Embedded system designers often face a large number of design alternatives when designing complex systems. A designer must select an alternative which satisfies application constraints (e.g. timing requirements) while optimizing system level objectives such as overall energy consumption. The size of design space is often very large giving rise to the need for systematic Design Space Exploration (DSE) methods. In this paper we address the DSE problem for real-time applications that belong to two different domains: (i) streaming applications modeled using the synchronous dataflow graphs; (ii) feedback control tasks modeled using the periodic task model. We consider a heterogeneous multiprocessor platform in which processors communicate through a predictable bus architecture. We present our DSE tool in which the DSE problem is modeled as a constraint satisfaction problem, and it is solved using a constraint programming solver. This approach provides a modular framework in which different constraints such as deadline, throughput and energy consumption can easily be plugged depending on the system being designed.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115695263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Vissers, J. Mengerink, R. Schiffelers, Alexander Serebrenik, M. Reniers
{"title":"Maintenance of specification models in industry using Edapt","authors":"Y. Vissers, J. Mengerink, R. Schiffelers, Alexander Serebrenik, M. Reniers","doi":"10.1109/FDL.2016.7880374","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880374","url":null,"abstract":"Domain specific languages (DSLs) ease the adoption of formal specification in industry. They allow developers to describe their specification models in concepts of their domain. However, DSLs evolve over time, causing specification models to have to co-evolve to reflect the evolution in the DSL. The maintenance overhead introduced by these, often manual, changes to specification models threatens to overshadow the advantages of DSL usage in industry. To this extent, many approaches have been proposed in the literature to facilitate DSL maintenance by automating model co-changes. In this paper, we evaluate the ability of a tool, Edapt, to support the change and co-change in twenty-two industrial DSLs and corresponding specification models over a maintenance period of four years. We observe that the tool is only able to automatically co-change specification models for 72% of the DSL changes. To address the remaining 28% of the changes, we extend Edapt. The resulting extension allows automatically co-changing specification models for 98% of the DSL changes.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115274205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Equivalence checking on ESL utilizing a priori knowledge","authors":"N. Thole, Heinz Riener, G. Fey","doi":"10.1109/FDL.2016.7880367","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880367","url":null,"abstract":"We propose EASY, an algorithm for functional equivalence checking of ESL descriptions written in a high-level programming language like C++. Given two ESL descriptions, in a PDR-like fashion EASY systematically refines a candidate invariant to characterize the reachable states of a miter of the descriptions until either the invariant becomes inductive or a counterexample has been found. The algorithm is flexible and allows to incorporate a priori knowledge about the design to speed up the verification process. We provide an implementation of EASY on top of a standard model checker and show in two case studies that EASY outperforms other state-of-the-art equivalence checking tools.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130586500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gadi Aleksandrowicz, E. Arbel, R. Bloem, Timon D. ter Braak, S. Devadze, G. Fey, M. Jenihhin, A. Jutman, H. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, J. Raik, G. Rauwerda, Heinz Riener, Franz Röck, K. Shibin, K. Sunesen, J. Wan, Yong Zhao
{"title":"Designing reliable cyber-physical systems overview associated to the special session at FDL'16","authors":"Gadi Aleksandrowicz, E. Arbel, R. Bloem, Timon D. ter Braak, S. Devadze, G. Fey, M. Jenihhin, A. Jutman, H. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, J. Raik, G. Rauwerda, Heinz Riener, Franz Röck, K. Shibin, K. Sunesen, J. Wan, Yong Zhao","doi":"10.1109/FDL.2016.7880382","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880382","url":null,"abstract":"CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131791452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models","authors":"S. Vinco, M. Lora, E. Macii, M. Poncino","doi":"10.1109/FDL.2016.7880379","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880379","url":null,"abstract":"Smart systems are miniaturized devices integrating computation, communication, sensing and actuation. As such, their design can not focus solely on functional behavior, but it must rather take into account different extra-functional concerns, such as power consumption or reliability. Any smart system can thus be modeled through a number of views, each focusing on a specific concern. Such views may exchange information, and they must thus be simulated simultaneously to reproduce mutual influence of the corresponding concerns. This paper shows how the IP-XACT standard, with some necessary extensions, can effectively support this simultaneous simulation. The extended IP-XACT descriptions allow to model extra-functional properties with a homogeneous format, defined by analysing requirements and characteristic of three main concerns, i.e., power, temperature and reliability. The IP-XACT descriptions are then used to automatically generate a skeleton of the simulation infrastructure in SystemC. The skeleton can be easily populated with models available in the literature, thus reaching simultaneous simulation of multiple concerns.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115224522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}