2016 Forum on Specification and Design Languages (FDL)最新文献

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Error-free near-threshold adiabatic CMOS logic in presence of process variation 无误差近阈值绝热CMOS逻辑存在工艺变化
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880381
Yue Lu, T. Kazmierski
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引用次数: 0
Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients 组合电路对单事件瞬变脆弱性的综合非功能分析
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880371
Ghaith Bany Hamad, Ghaith Kazma, O. Mohamed, Y. Savaria
{"title":"Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients","authors":"Ghaith Bany Hamad, Ghaith Kazma, O. Mohamed, Y. Savaria","doi":"10.1109/FDL.2016.7880371","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880371","url":null,"abstract":"The progressive shrinking of device sizes in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to different types of uncertainties, parametric variations, and interference. In this paper, we propose a methodology to model and analyze the behavior of a system in the presence of Single Event Transients (SETs). The problem of SET propagation was modeled as a satisfiability problem using different satisfiability modulo theories. The SET width and timing constraints are formulated as a difference logic constraint satisfaction formulation. This formulation utilizes concepts from static timing analysis to efficiently evaluate the required time and width for the SET to be latched. Next, the proposed model is analyzed using efficient SMT solvers for a set of nonfunctional assertions to investigate SETs propagation. Based on the results of this analysis, new fault observability estimates are computed. These values are then used to compute the soft error rate. Experimental results demonstrate that the proposed SMT approach provides better runtime then contemporary techniques.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126662836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automated synthesis of cyber-physical systems from joint controller/architecture specifications 从联合控制器/架构规范自动合成网络物理系统
2016 Forum on Specification and Design Languages (FDL) Pub Date : 2016-09-01 DOI: 10.1109/FDL.2016.7880389
Debayan Roy, Licong Zhang, Wanli Chang, S. Chakraborty
{"title":"Automated synthesis of cyber-physical systems from joint controller/architecture specifications","authors":"Debayan Roy, Licong Zhang, Wanli Chang, S. Chakraborty","doi":"10.1109/FDL.2016.7880389","DOIUrl":"https://doi.org/10.1109/FDL.2016.7880389","url":null,"abstract":"One emerging research direction to address the design of Cyber-Physical Systems (CPS) is the co-design of the architecture and the controllers. The co-design techniques integrate the design of control and architecture in an early phase and the parameters on both sides can be synthesized according to certain design objectives. This explores the characteristics on both sides to achieve more efficient design of such systems. In this paper, we give an overview of the automated synthesis of CPS from joint controller/architecture specifications by explaining the background and motivation for such methods and illustrating this design paradigm with a concrete example of a FlexRay-based embedded control system. Furthermore, we provide the future outlook in this direction by explaining possible extensions and the related challenges.","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125796630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Knowing your AMS system's limits: system acceptance region exploration by using automated model refinement and accelerated simulation 了解您的AMS系统的限制:通过使用自动模型细化和加速仿真来探索系统接受区域
2016 Forum on Specification and Design Languages (FDL) Pub Date : 1900-01-01 DOI: 10.1007/978-3-319-62920-9_1
G. Glaser, Hyun-Sek Lukas Lee, M. Olbrich, E. Barke
{"title":"Knowing your AMS system's limits: system acceptance region exploration by using automated model refinement and accelerated simulation","authors":"G. Glaser, Hyun-Sek Lukas Lee, M. Olbrich, E. Barke","doi":"10.1007/978-3-319-62920-9_1","DOIUrl":"https://doi.org/10.1007/978-3-319-62920-9_1","url":null,"abstract":"","PeriodicalId":137305,"journal":{"name":"2016 Forum on Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130530652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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