Error-free near-threshold adiabatic CMOS logic in presence of process variation

This paper provides the first analysis of process variation effect on the adiabatic logic combined with nearthreshold operation. One of the significant concerns is whether reliable performance is retained. We find that typical variations of process parameters do not affect error-free operation at the minimum-energy frequency. Monte Carlo simulations of a 4- bit full adder using ECRL logic with 0.45 V supply voltage show that, in the presence of typical process variations, energy consumption of the circuit operating at 25 MHz increases by 10.2% in the worst case while a 100% error-free operation is maintained. The maximum operating frequency(208 MHz) is reduced to nearly half of the nominal value(385 MHz). To further improve the robustness of the adder against process variation, a bit-serial adiabatic adder is considered with an even lower energy consumption per cycle.