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ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)最新文献

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A simple method for formation of the buffer layer in n-channel LDMOS 一种在n沟道LDMOS中形成缓冲层的简单方法
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820971
Pyung-Moon Zhang, Oh-Khong Kwon
{"title":"A simple method for formation of the buffer layer in n-channel LDMOS","authors":"Pyung-Moon Zhang, Oh-Khong Kwon","doi":"10.1109/ICVC.1999.820971","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820971","url":null,"abstract":"We propose a simple and cost-effective process of die buffer region which enhances the safe operation area (SOA) of the lateral double diffused MOSFETs (LDMOSFETs). Field oxide used for LOCOS isolation in conventional low voltage CMOS process is grown selectively around n+ drain of LDMOSFETs, which acts as buffer region around n+ drain with the help of dopant redistribution at silicon surface. The 150 V rating n-channel LDMOSFETs optimized using the proposed method have the best-reported specific on-resistance of 3.91 m/spl Omega/ cm/sup 2/ and higher second breakdown voltage by 20 V than that of conventional LDMOSFETs.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"30 1","pages":"469-472"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88224785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improved etching technique of E-ICP (Enhanced Inductively Coupled Plasma) 改进的E-ICP(增强电感耦合等离子体)刻蚀技术
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820958
Jae-Seong Jeong, O. Beom-hoan, Se-Guen Park
{"title":"Improved etching technique of E-ICP (Enhanced Inductively Coupled Plasma)","authors":"Jae-Seong Jeong, O. Beom-hoan, Se-Guen Park","doi":"10.1109/ICVC.1999.820958","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820958","url":null,"abstract":"A novel technique, named as \"Enhanced-ICP\", for a better etch process, has been proposed. Here, we report an improved result of the E-ICP. A photo-resist etch uniformity of below 1% within 10 cm in diameter has been accomplished with improved plasma density and the low electron temperature of 1 eV.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"273 1","pages":"441-443"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86729038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of full chip OPC to quarter micron logic device 全片OPC在四分之一微米逻辑器件中的应用
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820864
Kyune-Jin Shim, Ki-yeop Park, Won Gyu Lee, Dai-Hoon Lee
{"title":"Application of full chip OPC to quarter micron logic device","authors":"Kyune-Jin Shim, Ki-yeop Park, Won Gyu Lee, Dai-Hoon Lee","doi":"10.1109/ICVC.1999.820864","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820864","url":null,"abstract":"Model based full chip Optical Proximity Correction (OPC) was applied to logic devices with a minimum gate length of 0.24 /spl mu/m. Two empirical models were used in order to correct for both the 1D optical proximity effect and the 2D optical proximity effect simultaneously. OPC features such as line bias and hammer head were effective in reducing critical dimension variation and line shortening. Increased process margin and reduction in interconnection resistance were obtained.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"517 1","pages":"171-173"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91527849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of low-temperature N/sub 2/O-annealed oxide and chemical oxide for both boron penetration and gate depletion reductions for thin p/sup +/ tungsten polycide gate 低温N/sub - 2/ o退火氧化物和化学氧化物在p/sup +/钨多晶硅薄栅中硼渗透和栅损耗的应用
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820891
Yunseok Chun, Kwang Pyo Lee, Sang Su Lee, Sang Chul Kim, Byung-Seop Hong, Hong Yang
{"title":"Application of low-temperature N/sub 2/O-annealed oxide and chemical oxide for both boron penetration and gate depletion reductions for thin p/sup +/ tungsten polycide gate","authors":"Yunseok Chun, Kwang Pyo Lee, Sang Su Lee, Sang Chul Kim, Byung-Seop Hong, Hong Yang","doi":"10.1109/ICVC.1999.820891","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820891","url":null,"abstract":"Boron behavior in p/sup +/ W-polycide gate used for high performance surface-channel pMOSFET was investigated. The poly structure and poly-WSi/sub x/ interface play an important role in the characteristics of the MOSFET. It was found that large-grain poly showed severe boron penetration compared to an 800 /spl Aring/ amorphous Si layer. In addition, boron out-diffusion into the WSi/sub x/ layer causes severe gate depletion which gives rise to low saturation current. Application of chemical oxide between poly and tungsten silicide turns out to be good barrier to block fluorine diffusion into the gate oxide as well as boron out-diffusion into the WSi/sub x/ layer. A surface channel pMOSFET using N/sub 2/O-annealed oxide and chemical oxide shows excellent characteristics of high saturation current, low leakage and gate depletion.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"23 1","pages":"237-240"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84625225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A digital temperature compensated crystal oscillator using a temperature adaptive capacitor array 采用温度自适应电容阵列的数字温度补偿晶体振荡器
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820900
M. Je, Joonho Gil, Jaeyoung Kwak, H. Yoo, Hyungcheol Shin
{"title":"A digital temperature compensated crystal oscillator using a temperature adaptive capacitor array","authors":"M. Je, Joonho Gil, Jaeyoung Kwak, H. Yoo, Hyungcheol Shin","doi":"10.1109/ICVC.1999.820900","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820900","url":null,"abstract":"We propose a new capacitor array scheme that we call a temperature adaptive capacitor array (TACA) and use it to achieve complete digital trimming of the TCXO at 20 MHz with 0.3 ppm trimming accuracy. The TACA scheme guarantees monotonicity and saves silicon area at the same time. About 10 % reduction in array layout area and about 14 % reduction in the pre-decoding logic area are reported.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"60 1","pages":"263-265"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90629496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter 基于低功耗低纹波DC-DC转换器的3v 200mhz低噪声压控振荡器锁相环
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820928
Seung-Chul Lee, Joon-seok Lee, Sung-Ho Lee, Seunghoon Lee
{"title":"A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter","authors":"Seung-Chul Lee, Joon-seok Lee, Sung-Ho Lee, Seunghoon Lee","doi":"10.1109/ICVC.1999.820928","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820928","url":null,"abstract":"This paper describes a phase-locked loop (PLL) clock generator with low sensitivity to power supply noise. A voltage controlled oscillator employing a source follower reduces power supply noise sensitivity with the proposed power-efficient low-ripple DC-DC converter. Simulated clock jitter is less than /spl plusmn/20 ps, with a 200 mV peak-to-peak sinusoidal noise signal of 1 MHz to 400 MHz applied to a power supply. The proposed PLL simulated in a 0.65 /spl mu/m double-poly double-metal CMOS process consumes 27 mW at 200 MHz from a 3 V supply. The prototype is under fabrication.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"1 1","pages":"346-348"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90124098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental stress analysis for flip chip BGA packages using strain gauge 用应变计分析倒装BGA封装的实验应力
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820988
H. Moon, T.G. Chung, H. Lee, E. Ahn, T. Cho, S.Y. Oh
{"title":"Experimental stress analysis for flip chip BGA packages using strain gauge","authors":"H. Moon, T.G. Chung, H. Lee, E. Ahn, T. Cho, S.Y. Oh","doi":"10.1109/ICVC.1999.820988","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820988","url":null,"abstract":"The application of a flip chip ball grid array (BGA) package with organic substrate in electronic devices has significantly grown during the past few years. However, potential package reliability problems can still occur, for example die cracks, underfill cracks, and solder joint cracks. An experimental stress analysis which is to measure the stress distribution at the flip chip BGA package using strain gauge and finite element analysis were performed to predict the susceptibility of die cracking during thermal cyclic loading. The experimental stress analysis which is the in-situ stress measurement technique was applied for different variables such as chip thickness, organic substrate and underfill materials. The stress distribution was measured on four kinds of flip chip BGA packages. These results were also compared with the reliability data of package level in order to verify its effectiveness. From the above results, we can find that the strain behavior of the flip chip BGA package with temperature is nonlinear. It also reveals that the strain measured at the lowest temperature is not the maximum. Finally, we can conclude that the experimental stress analysis is a very useful method to predict the susceptibility of die tracking during the thermal cyclic loading in flip chip BGA packages.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"8 1","pages":"510-513"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90359837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
40 nm electron beam patterning and its application to silicon nano-structure fabrication 40nm电子束成像及其在硅纳米结构制造中的应用
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820860
Sangyeon Han, Taejnn Park, Bonkee Kim, Hyungcheol Shin, Kwyro Lee
{"title":"40 nm electron beam patterning and its application to silicon nano-structure fabrication","authors":"Sangyeon Han, Taejnn Park, Bonkee Kim, Hyungcheol Shin, Kwyro Lee","doi":"10.1109/ICVC.1999.820860","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820860","url":null,"abstract":"We report on 40 nm patterning using an E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of the E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 /spl mu/m. In this way, PEB (Post Expose Bake) time and temperature, which are very important factors for nanopatterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wires, quantum dots, and quantum dots on a narrow channel, which can be used for nano-scale memory devices (such as single electron memory devices), were fabricated using these lithography techniques.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"11 1","pages":"163-166"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88860503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a combined processor containing a 32-bit RISC microprocessor and a 16-bit fixed-point DSP on a chip 一个包含32位RISC微处理器和16位定点DSP的组合式处理器的设计
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820913
Wookyeong Jeong, S. An, M. Kim, Sangkyong Heo, Youngju Kim, Sangook Moon, Yong-Surk Lee
{"title":"Design of a combined processor containing a 32-bit RISC microprocessor and a 16-bit fixed-point DSP on a chip","authors":"Wookyeong Jeong, S. An, M. Kim, Sangkyong Heo, Youngju Kim, Sangook Moon, Yong-Surk Lee","doi":"10.1109/ICVC.1999.820913","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820913","url":null,"abstract":"In this paper, a combined architecture, YS-RDSP, which merges a RISC microprocessor with a DSP processor to be suitable for embedded applications is proposed and designed. The YS-RDSP can execute maximum 4 instructions in parallel at the same time. In order to reduce the size of programs, the YS-RDSP has variable instruction length of 16-bit and 32-bit. The YS-RDSP provides DSP processing power as well as control power and programmability of RISC microprocessor on a single chip. The YS-RDSP has 8-kbyte ROM and 8-kbyte RAM on chip. System controller which is a peripheral included in the chip provides three power-down modes for low-power operations, and SLEEP instruction switches the operation states of the CPU core and peripherals. The YS-RDSP processor is modeled in Verilog-HDL with top-down design methodology. Verified model is synthesized with 0.6 /spl mu/m 3.3 V CMOS standard cell library and laid out using automated P&R resulting 10.7 mm by 8.4 mm core area.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"88 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89354176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Switched-capacitor circuit techniques in submicron low-voltage CMOS 亚微米低压CMOS开关电容电路技术
ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820929
U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, F. Maloberti
{"title":"Switched-capacitor circuit techniques in submicron low-voltage CMOS","authors":"U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, F. Maloberti","doi":"10.1109/ICVC.1999.820929","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820929","url":null,"abstract":"The continued down scaling of submicron CMOS technology forces innovation of practical and economical circuits that will tolerate reduced headroom (reduced power supply voltage) due to lowering of the technology's maximum allowable voltage. Given the relatively large threshold voltages with respect to the shrinking headroom, a group of widely used analog signal processing building blocks that are made of switched-capacitor (SC) stages will encounter severe overdrive problems when operating at these low-voltage conditions. This tutorial summarizes some of the well-known solutions currently in use and problems associated with these solutions, and proposes novel circuit techniques for truly low-voltage switched-capacitor applications.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"50 1","pages":"349-358"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87375381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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