A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors

Abstract

In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops.