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IEEE Journal of Solid-state Circuits最新文献

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A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology 基于多dtc拓扑的低抖动分数n数字锁相环与杂散抵消
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-25 DOI: 10.1109/jssc.2025.3560870
Giacomo Castoro, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
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引用次数: 0
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead 采用NMOS头辅助单元的14纳米SRAM，以最小的功耗开销提高了写入能力并减少了单元保留泄漏
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-25 DOI: 10.1109/jssc.2025.3562400
Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Sei Seung Yoon, Seong-Ook Jung
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引用次数: 0
A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique 基于自适应频率滤波技术的低杂散低抖动分数输出分频器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-25 DOI: 10.1109/jssc.2025.3561203
Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi
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引用次数: 0
IEEE Journal of Solid-State Circuits Information for Authors IEEE固态电路杂志作者信息
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI: 10.1109/JSSC.2025.3562410
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引用次数: 0
IEEE Journal of Solid-State Circuits Publication Information IEEE固态电路杂志出版信息
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI: 10.1109/JSSC.2025.3555370
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引用次数: 0
Guest Editorial: Introduction to the Special Section on the 2024 RFIC Symposium 嘉宾评论：2024年RFIC研讨会专题介绍
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI: 10.1109/JSSC.2025.3554346
Wanghua Wu
{"title":"Guest Editorial: Introduction to the Special Section on the 2024 RFIC Symposium","authors":"Wanghua Wu","doi":"10.1109/JSSC.2025.3554346","DOIUrl":"https://doi.org/10.1109/JSSC.2025.3554346","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1515-1515"},"PeriodicalIF":4.6,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10976337","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation” 修正“使用数字杂散抵消的<90-fs抖动和<-103-dBc杂散音的分数频率合成器的设计和分析”
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI: 10.1109/JSSC.2025.3550254
Mohammadreza Zeinali;Sudhakar Pamarti
{"title":"Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”","authors":"Mohammadreza Zeinali;Sudhakar Pamarti","doi":"10.1109/JSSC.2025.3550254","DOIUrl":"10.1109/JSSC.2025.3550254","url":null,"abstract":"This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the overall validity of the results, and the main conclusions of the original article remain unchanged.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1882-1882"},"PeriodicalIF":4.6,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10976338","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143873017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TechRxiv: Share Your Preprint Research With the World! techxiv：与世界分享你的预印本研究！
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI: 10.1109/JSSC.2025.3562412
{"title":"TechRxiv: Share Your Preprint Research With the World!","authors":"","doi":"10.1109/JSSC.2025.3562412","DOIUrl":"10.1109/JSSC.2025.3562412","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1883-1883"},"PeriodicalIF":4.6,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10976346","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143873016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS 采用 28 纳米 CMOS 的 29.12-TOPS/W 矢量收缩加速器与 NAS 优化的 DNN
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-22 DOI: 10.1109/jssc.2025.3558287
Kai Li, Mingqiang Huang, Ang Li, Shuxin Yang, Quan Cheng, Hao Yu
{"title":"A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS","authors":"Kai Li, Mingqiang Huang, Ang Li, Shuxin Yang, Quan Cheng, Hao Yu","doi":"10.1109/jssc.2025.3558287","DOIUrl":"https://doi.org/10.1109/jssc.2025.3558287","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"12 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143862103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
How to Keep Pushing ML Accelerator Performance? Know Your Rooflines! 如何继续推动ML加速器性能？了解你的底线！
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-21 DOI: 10.1109/jssc.2025.3553765
Marian Verhelst, Luca Benini, Naveen Verma
{"title":"How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!","authors":"Marian Verhelst, Luca Benini, Naveen Verma","doi":"10.1109/jssc.2025.3553765","DOIUrl":"https://doi.org/10.1109/jssc.2025.3553765","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"108 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143858019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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