具有参考嵌入时域残数的混合电压-时域流水线ADC

IF 4.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-06-24 DOI:10.1109/jssc.2025.3579913

Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-Il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn

引用次数: 0

摘要

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.