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IEEE Journal of Solid-state Circuits最新文献

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A Multi-Band RF Transmitter Employing a Transformer-Based N-Path Switched-Capacitor Modulator for CIM3 Suppression 采用变压器 N 路径开关电容调制器抑制 CIM3 的多波段射频发射机
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-11 DOI: 10.1109/jssc.2025.3557459
Gengzhen Qi, Pui-In Mak
{"title":"A Multi-Band RF Transmitter Employing a Transformer-Based N-Path Switched-Capacitor Modulator for CIM3 Suppression","authors":"Gengzhen Qi, Pui-In Mak","doi":"10.1109/jssc.2025.3557459","DOIUrl":"https://doi.org/10.1109/jssc.2025.3557459","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Phase-Scalable CF-Cross-Connected-Based Hybrid DC–DC Converter With Auto VCF Balancing and Inactive CF Charging 具有自动 VCF 平衡和非活动 CF 充电功能的可相位扩展 CF 交叉连接型混合 DC-DC 转换器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-11 DOI: 10.1109/jssc.2025.3557060
Jiacheng Yang, Tingxu Hu, Yan Lu, Xin Ming, Rui P. Martins, Mo Huang
{"title":"Phase-Scalable CF-Cross-Connected-Based Hybrid DC–DC Converter With Auto VCF Balancing and Inactive CF Charging","authors":"Jiacheng Yang, Tingxu Hu, Yan Lu, Xin Ming, Rui P. Martins, Mo Huang","doi":"10.1109/jssc.2025.3557060","DOIUrl":"https://doi.org/10.1109/jssc.2025.3557060","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"27 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56fmax: An Analytical Approach on Reversed Feedback Amplifiers
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-11 DOI: 10.1109/jssc.2025.3554814
Saleh Hassanzadehyamchi, Amirreza Alizadeh, Omeed Momeni, Ali M. Niknejad
{"title":"Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56fmax: An Analytical Approach on Reversed Feedback Amplifiers","authors":"Saleh Hassanzadehyamchi, Amirreza Alizadeh, Omeed Momeni, Ali M. Niknejad","doi":"10.1109/jssc.2025.3554814","DOIUrl":"https://doi.org/10.1109/jssc.2025.3554814","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"75 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-11 DOI: 10.1109/jssc.2025.3556649
Xuyang Liu, Md. Hedayatullah Maktoomi, Mahdi Alesheikh, Payam Heydari, Hamidreza Aghasi
{"title":"A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver","authors":"Xuyang Liu, Md. Hedayatullah Maktoomi, Mahdi Alesheikh, Payam Heydari, Hamidreza Aghasi","doi":"10.1109/jssc.2025.3556649","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556649","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"16 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3552590
Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue
{"title":"A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS","authors":"Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue","doi":"10.1109/jssc.2025.3552590","DOIUrl":"https://doi.org/10.1109/jssc.2025.3552590","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"183 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.00175 mm2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3555007
Roman Willaredt, Christoph Grandauer, Daniel De Dorigo, Matthias Kuhl, Yiannos Manoli
{"title":"A 0.00175 mm2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm","authors":"Roman Willaredt, Christoph Grandauer, Daniel De Dorigo, Matthias Kuhl, Yiannos Manoli","doi":"10.1109/jssc.2025.3555007","DOIUrl":"https://doi.org/10.1109/jssc.2025.3555007","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"25 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS 在 28-nm CMOS 中实现占空比开关 30-Gb/s 突发模式 CDR，锁定时间为 1.6-ns
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556524
Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs
{"title":"A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS","authors":"Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs","doi":"10.1109/jssc.2025.3556524","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556524","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"74 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction 基于粘合剂贴片机的可重构多传感器贴片接口，具有片上量化时域特征提取功能
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556441
You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim
{"title":"An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction","authors":"You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim","doi":"10.1109/jssc.2025.3556441","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556441","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"105 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3555383
Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
{"title":"A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS","authors":"Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu","doi":"10.1109/jssc.2025.3555383","DOIUrl":"https://doi.org/10.1109/jssc.2025.3555383","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"442 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3556123
Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee
{"title":"An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory","authors":"Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee","doi":"10.1109/jssc.2025.3556123","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556123","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"24 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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