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IEEE Journal of Solid-state Circuits最新文献

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A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS 在 28-nm CMOS 中实现占空比开关 30-Gb/s 突发模式 CDR，锁定时间为 1.6-ns
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556524
Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs
{"title":"A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS","authors":"Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs","doi":"10.1109/jssc.2025.3556524","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556524","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"74 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction 基于粘合剂贴片机的可重构多传感器贴片接口，具有片上量化时域特征提取功能
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556441
You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim
{"title":"An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction","authors":"You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim","doi":"10.1109/jssc.2025.3556441","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556441","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"105 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS 基于抖动滤波时钟和误码率优化技术的122gb /s PAM-4重定时器收发器
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/JSSC.2025.3555383
Hua Xu;Mingche Lai;Xuqiang Zheng;Zedong Wang;Jiang Xu;Sai Li;Fangxu Lv;Min Liu;Weijie Li;Zhanhao Wen;Xuan Guo;Xinhua Wang;Zhi Jin;Xinyu Liu
{"title":"A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS","authors":"Hua Xu;Mingche Lai;Xuqiang Zheng;Zedong Wang;Jiang Xu;Sai Li;Fangxu Lv;Min Liu;Weijie Li;Zhanhao Wen;Xuan Guo;Xinhua Wang;Zhi Jin;Xinyu Liu","doi":"10.1109/JSSC.2025.3555383","DOIUrl":"10.1109/JSSC.2025.3555383","url":null,"abstract":"This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) analog-to-digital converter (ADC)-digital signal processing (DSP)-based retimer transceiver for reaching-distance extension. An injection-locked oscillator (ILO)-based jitter-filtering clocking scheme with relaxed bandwidth limitation and low-power consumption is proposed to obtain synchronous low-jitter clocks. The transmitter (TX) utilizes an internal feed-forward equalizer (FFE) cascaded with a forward-coupling pad driver to improve the output inter-symbol interference (ISI) jitter, and a timing-optimized 4:1 multiplexer (MUX) to reduce the serialization jitter. The receiver (RX) combines a flexible continuous-time linear equalizer (CTLE), a signal-to-noise ratio (SNR)-optimized ADC with 8-bit quantization, and a high-resolution digital equalization to further minimize the bit-error rate (BER). Fabricated in a 28-nm CMOS process, the prototype transceiver achieves 1E-12 raw BER at 112 Gb/s while compensating 31.2-dB channel loss. The clock network delivers a rms recovered clock jitter of 252 fs and a power efficiency of 0.56 pJ/bit, which outperforms other state-of-the-art works.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2305-2318"},"PeriodicalIF":4.6,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory 基于IGZO tft的6T1C突触记忆模拟神经形态片上训练系统
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3556123
Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee
{"title":"An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory","authors":"Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee","doi":"10.1109/jssc.2025.3556123","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556123","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"24 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping 用于多方案读取映射的28纳米239bp /μJ敏捷泛基因组分析加速器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3554616
Yichi Zhang, Jianfeng Zhu, Liangwei Li, Gang Zeng, Dibei Chen, Tairan Zhang, Yeyang Deng, Zhicheng Gong, Aoyang Zhang, Yang Liu, Shaojun Wei, Leibo Liu
{"title":"A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping","authors":"Yichi Zhang, Jianfeng Zhu, Liangwei Li, Gang Zeng, Dibei Chen, Tairan Zhang, Yeyang Deng, Zhicheng Gong, Aoyang Zhang, Yang Liu, Shaojun Wei, Leibo Liu","doi":"10.1109/jssc.2025.3554616","DOIUrl":"https://doi.org/10.1109/jssc.2025.3554616","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"37 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision 一种8位精度的65nm数字随机内存计算CNN处理器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-07 DOI: 10.1109/jssc.2025.3554554
Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti
{"title":"A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision","authors":"Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti","doi":"10.1109/jssc.2025.3554554","DOIUrl":"https://doi.org/10.1109/jssc.2025.3554554","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"18 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143797917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS 55纳米CMOS中基于多端口达灵顿单元的19- 45 GHz高效倍频器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-04 DOI: 10.1109/jssc.2025.3553760
Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao, Kaixue Ma
{"title":"A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS","authors":"Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao, Kaixue Ma","doi":"10.1109/jssc.2025.3553760","DOIUrl":"https://doi.org/10.1109/jssc.2025.3553760","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"108 1","pages":"1-16"},"PeriodicalIF":5.4,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143782435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 470-μW, 102.6-dB DR, 20-kHz BW Calibration-Free Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC 一种470 μ w， 102.6 db DR, 20khz BW， SFDR超过110 dBc的免校准调制器，采用本质线性13级DAC
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-04 DOI: 10.1109/jssc.2025.3553310
Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns
{"title":"A 470-μW, 102.6-dB DR, 20-kHz BW Calibration-Free Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC","authors":"Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns","doi":"10.1109/jssc.2025.3553310","DOIUrl":"https://doi.org/10.1109/jssc.2025.3553310","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"132 1","pages":"1-0"},"PeriodicalIF":5.4,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143782458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and −100 dBc IM3 for a Mixer-Less DAB Band III Receiver 6 ghz连续时间带通TEXPRESERVE0 ADC，带背景滤波器校准和-100 dBc IM3，用于无混频器DAB Band III接收器
IF 4.6 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-03 DOI: 10.1109/JSSC.2025.3553045
Shagun Bajoria;Robert Rutten;Muhammed Bolatkale;Yihan Gao;Hans Brekelmans;Bernard Burdiek;Hendrik Van Der Ploeg;Lucien J. Breems
{"title":"A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and −100 dBc IM3 for a Mixer-Less DAB Band III Receiver","authors":"Shagun Bajoria;Robert Rutten;Muhammed Bolatkale;Yihan Gao;Hans Brekelmans;Bernard Burdiek;Hendrik Van Der Ploeg;Lucien J. Breems","doi":"10.1109/JSSC.2025.3553045","DOIUrl":"10.1109/JSSC.2025.3553045","url":null,"abstract":"This article presents a 6-GHz continuous-time bandpass (BP) delta-sigma analog-to-digital converter (ADC) that has been designed for a mixer-less automotive digital audio broadcasting (DAB) III broadcast radio receiver in 28-nm CMOS. The BP ADC can directly digitize the entire DAB III band from 174 to 240 MHz without the need for analog mixers. A precise temperature tracking background calibration guarantees high reception quality over process, voltage and temperature (PVT). The measured IM3 is −100 dBc with two input tones at 210 and 220 MHz, respectively. FM intrusion with a 92 MHz input signal is −101.7 dBc.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2284-2293"},"PeriodicalIF":4.6,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143775480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning 具有二次谐波源调谐功能的宽带太赫兹推推倍频器的分析与设计
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-03 DOI: 10.1109/jssc.2025.3553750
Shuyang Li, Xingcun Li, Huibo Wu, Yunfan Wang, Shouqing Fu, Xin Liu, Wenhua Chen
{"title":"Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning","authors":"Shuyang Li, Xingcun Li, Huibo Wu, Yunfan Wang, Shouqing Fu, Xin Liu, Wenhua Chen","doi":"10.1109/jssc.2025.3553750","DOIUrl":"https://doi.org/10.1109/jssc.2025.3553750","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"15 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143775481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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