IEEE Journal of Solid-state Circuits最新文献_第10页

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-23 DOI: 10.1109/jssc.2025.3529715

Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits

引用次数: 0

2024 Index IEEE Journal of Solid-State Circuits Vol. 59 IEEE固体电路学报，第59卷

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-22 DOI: 10.1109/JSSC.2025.3529116

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An E-Band FMCW Radar Receiver With Arbitrary-Path Spillover Cancellation 一种具有任意路径溢出抵消的e波段FMCW雷达接收机

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-17 DOI: 10.1109/jssc.2025.3527072

Bolin Chen, Zhirui Zong

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Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET 基于PNP bjt的紧凑型温度传感器和Sub-1-V带隙参考元件，用于4nm FinFET的SoC应用

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-16 DOI: 10.1109/jssc.2024.3524245

You Li, David E. Duarte, James S. Ayers, Yongping Fan

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A Closed-Loop EMI Regulated GaN Power Converter With In Situ EMI Sensing and Global Excess-Spectrum Modulation 具有原位电磁干扰传感和全局过量频谱调制的闭环电磁干扰调节氮化镓功率变换器

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-16 DOI: 10.1109/JSSC.2025.3527075

Yingping Chen;Qing Yuan;Ming Liu

{"title":"A Closed-Loop EMI Regulated GaN Power Converter With In Situ EMI Sensing and Global Excess-Spectrum Modulation","authors":"Yingping Chen;Qing Yuan;Ming Liu","doi":"10.1109/JSSC.2025.3527075","DOIUrl":"10.1109/JSSC.2025.3527075","url":null,"abstract":"As electromagnetic interference (EMI) standards evolve from the rules-based approach to the risk-based alternate, online EMI assessment and control become critical for lifetime risk management. With such a trend, this article presents an online closed-loop EMI regulation for gallium-nitride (GaN) power converter. Specifically, a wide-bandwidth in situ EMI sensor is integrated to characterize the noise through autocovariance-based spectrum analysis. A stepwise random space sampling (SRSS) significantly compresses the sensing time without sacrificing the accuracy for real-time EMI spectral characterization. Based on the online measured noise, a global excess-spectrum modulator is devised to adaptively track, and hence, continuously regulate the maximum excess noise. A prototype chip was fabricated in a 180-nm BCD process, commanding two enhancement-mode GaN power switches at a nominal frequency of 2.8 MHz. The measurement results show that the integrated in situ EMI sensor can capture the EMI spectra with a 500-MHz sampling bandwidth and 1-mV sensing accuracy while reducing the sensing time by over 25 times. Compared to the commercial spectrum analyzer, it demonstrates a maximum discrepancy of 3 dB. The embedded global excess-spectrum modulator accomplishes a 9-kHz-resolution EMI regulation, dynamically optimizing the EMI control.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 3","pages":"883-893"},"PeriodicalIF":4.6,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142987367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Bidirectional USB Power Delivery Voltage-Regulating Cable USB双向供电稳压电缆

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-16 DOI: 10.1109/jssc.2025.3527038

Zhiguo Tong, Junwei Huang, Xiangyu Mao, Rui P. Martins, Yan Lu

引用次数: 0

An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths 具有LC - DTC和混合比例路径的超低抖动快跳分数n锁相环

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-16 DOI: 10.1109/JSSC.2024.3514870

Hongzhuo Liu;Wei Deng;Haikun Jia;Zhihua Wang;Baoyong Chi

{"title":"An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths","authors":"Hongzhuo Liu;Wei Deng;Haikun Jia;Zhihua Wang;Baoyong Chi","doi":"10.1109/JSSC.2024.3514870","DOIUrl":"10.1109/JSSC.2024.3514870","url":null,"abstract":"This work presents an ultra-low-jitter fractional-N PLL capable of wideband fast hopping. There is an analog proportional path and a digital proportional/integral path in the PLL. The PLL is digital-path-dominant during settling and analog-path-dominant after settles; therefore, the fast-lock characteristic of the digital PLLs and the low-jitter characteristic of the analog PLLs are achieved. The frequency switching algorithm does not rely on the linearity of DCO’s tuning curve, nor rely on the hopping step between the previously locked frequency and the target frequency. The frequency detection is based on a high-speed counter, which uses the quadruple timing margin selection and can operate up to 20 GHz. The counter is integrated with a feedback clock generator, which is functionally the same as a multi-modulus divider. In addition, this work proposes an LC delay circuit as the coarse digital-to-time converter (DTC), which has better potential than the RC-based counterparts to reduce the phase noise of DTC and thereby reduce the jitter of fractional-N PLLs. The prototype is implemented in 28-nm CMOS process and occupies 0.21-mm2 core area. The measured hopping time is <inline-formula> <tex-math>$0.52~{mu }$ </tex-math></inline-formula>s across a 3.5-GHz step with 80-ppm settling accuracy. The measured rms jitter (integrated from 1 kHz to 100 MHz) is 36.8 fs for the integer-N channel, 41.3 fs for the far-integer fractional-N channel, and 61.7 fs for the near-integer fractional-N channel. The measured near-integer fractional spur is -62.4 dBc. The measured power consumption is 34 mW.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 3","pages":"785-798"},"PeriodicalIF":4.6,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142987369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden 5-MS/s 16位低噪声、低功耗分割采样SAR ADC

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-16 DOI: 10.1109/JSSC.2025.3526595

Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Qiwei Zhao;Jie Yuan

{"title":"A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden","authors":"Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Qiwei Zhao;Jie Yuan","doi":"10.1109/JSSC.2025.3526595","DOIUrl":"10.1109/JSSC.2025.3526595","url":null,"abstract":"This article presents a 16-bit 5-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed split sampling (SS) technique. The SS decouples the sampling and conversion operations of the ADC, effectively addressing the tradeoff among the driving burden of the digital-to-analog converter (DAC), sampling noise, power, and bit-cycling speed. The SS consists of 2 20-pF sampling capacitors and a 1-pF DAC. The sampling capacitors sample the input with low noise and cancel the kT/C noise of the DAC, avoiding the preamplifier saturation issue and easing the noise aliasing. As the sampling capacitors track the input when the DAC is performing bit-cycling, the input driving is eased with the extended tracking time. The small DAC guarantees fast speed and low power. Moreover, statistical residue measurement (SRM) is employed to reduce the preamplifier’s noise and the quantization noise, efficiently improving the signal-to-noise-and-distortion ratio (SNDR) and the bit weight calibration accuracy. The ADC is fabricated in a 180-nm process and occupies an active area of 0.57 mm2. With the SS and SRM, the ADC samples at 5 MS/s and achieves a 93.7-dB SNDR with a 5.31-mW power consumption, yielding a high Schreier-figure-of-merit (FoM) of 180.4 dB.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 3","pages":"813-825"},"PeriodicalIF":4.6,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142987366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier 具有次采样锁相环和谐波增强倍频器的低抖动宽频域d频带频率合成器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-10 DOI: 10.1109/jssc.2024.3523474

Seohee Jung, Jaeho Kim, Jooeun Bang, Sarang Lee, Heein Yoon, Jaehyouk Choi

引用次数: 0

A 27–39-GHz VSWR-Resilient Compact True Power and Gain Sensor With Built-In Sensing Error Compensation for Integrated Power Amplifiers 一种用于集成功率放大器的27 - 39 ghz vswr弹性紧凑型真功率增益传感器，内置传感误差补偿

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-01-10 DOI: 10.1109/jssc.2025.3525958

Edward Liu, David Munzer, Jeongseok Lee, Jianping Zeng, Hua Wang

引用次数: 0