IEEE Journal of Solid-state Circuits最新文献_第10页

A Sub-Nanosecond Pulsed VCSEL Driver With PVT-Compensated Constant Current, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety 具有pvt补偿恒流、集成升压开关稳压器和1级激光眼安全的亚纳秒脉冲VCSEL驱动器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-04 DOI: 10.1109/jssc.2025.3539432

Ming Zhong, Yifan Wu, Yuan Li, Wei Chen, Miao Sun, Liujia Song, Shanyu Cui, Xuefeng Chen, Patrick Yin Chiang, Shenglong Zhuo, Tao Xia

引用次数: 0

Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators 使用并行双频振荡器的漂移补偿磁性生物传感器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-04 DOI: 10.1109/jssc.2025.3544256

Jui-Hung Sun, Constantine Sideris

引用次数: 0

Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications 用于5G NR FR2和NR- u多频段/多标准通信的22.6 ~ 73.9 GHz低噪声放大器设计与分析

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-04 DOI: 10.1109/jssc.2025.3545463

Zenglong Zhao, Xianghui Chen, Fanyi Meng, Zhen Yang, Bing Liu, Nengxu Zhu, Keping Wang, Kaixue Ma, Kiat Seng Yeo

引用次数: 0

A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control 基于静电力反馈控制的430 μA 68.2 db - snr 133- dbspll - aop CMOS-MEMS数字传声器

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-03 DOI: 10.1109/JSSC.2025.3531509

Jiaqi Dong;Qi Zhang;Xinwen Zhang;Yekan Chen;Yili Shen;Bo Zhao;Yuxuan Luo

{"title":"A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control","authors":"Jiaqi Dong;Qi Zhang;Xinwen Zhang;Yekan Chen;Yili Shen;Bo Zhao;Yuxuan Luo","doi":"10.1109/JSSC.2025.3531509","DOIUrl":"10.1109/JSSC.2025.3531509","url":null,"abstract":"This article introduces a high-acoustic-dynamic-range and low-power digital microphone based on the electrostatic force feedback control (EFFC). The proposed design adjusts the sensitivity of the micro-electro-mechanical system (MEMS) by adaptively biasing it at different input amplitudes, thereby extending the dynamic range (DR). The proposed adaptive biasing technique allows the induced electrostatic force to function as a mechanical gain prior to the analog front end (AFE), consequently relaxing the noise performance requirements of the readout electronics. A capacitive feedback (CFB) instrumentation amplifier (IA) with an adjustable gain is employed to effectively reduce the thermal noise introduced by the feedback resistor in conventional resistive feedback (RFB) IAs. A sub-sampling amplitude detector (SSAD) composed of cascaded low-order decimation filters is proposed to achieve efficient acoustic volume detection. The detection results are used to control a fast-settling predictive reference charge pump (PRCP). The PRCP adopts a closed-loop architecture to achieve accurate adjustable bias voltage, with the proposed prediction logic to significantly reduce the settling time. The proposed system achieves a signal-to-noise ratio (SNR) of 68.2 dB at 94 dBSPL and an acoustic overload point (AOP) of 133 dBSPL, with a current consumption of <inline-formula> <tex-math>$430~{mu }$ </tex-math></inline-formula>A at a clock frequency of 3.072 MHz. The measured acoustic DR is 107.2 dB.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1199-1209"},"PeriodicalIF":4.6,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143538917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 92.3%-Efficiency Switching-Mode Dual-Output Regulating Rectifier With Improved Link Adaptability for Wireless Power Transfer 一种改进链路适应性的92.3%效率开关双输出整流器用于无线电力传输

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-03 DOI: 10.1109/jssc.2025.3540596

Tianqi Lu, Sijun Du

引用次数: 0

A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS 基于Intel 4 CMOS掩模同构复合域的4.7 ~ 5.3 gb /s故障注入和抗侧信道攻击AES-256引擎

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-02-27 DOI: 10.1109/JSSC.2025.3541573

Raghavan Kumar;Sachin Taneja;Vivek De;Sanu K. Mathew

{"title":"A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS","authors":"Raghavan Kumar;Sachin Taneja;Vivek De;Sanu K. Mathew","doi":"10.1109/JSSC.2025.3541573","DOIUrl":"10.1109/JSSC.2025.3541573","url":null,"abstract":"Physical attacks such as fault-injection attacks (FIAs) and side-channel attacks (SCAs) offer powerful adversarial tools to malicious parties that severely degrade the security offered by cryptographic ciphers. Laser FIA mounted on an unprotected advanced encryption standard (AES)-256 engine in Intel 4 CMOS process demonstrates a minimum-traces-to-disclosure (MTD) of 37M encryptions to generate eight exploitable ciphertexts, reducing AES key search space to a single guess with differential fault analysis (DFA). Power SCA offers a more powerful tool, enabling extraction of all key bytes through correlation power analysis (CPA) of 25k current traces. In this article, we present a unified FIA and SCA-resistant AES-256 engine fabricated in Intel 4 CMOS. Redundant AES round computations using isomorphic GF(<inline-formula> <tex-math>$2{^{4}}$ </tex-math></inline-formula>)2 composite-field representations and reconfigurable byte dataflows enable real-time detection of corrupted ciphertext with a fault-coverage of 99.3% and <inline-formula> <tex-math>$143{times }$ </tex-math></inline-formula> improvement in MTD while limiting area overhead to 12%. FIA-resistant configurations with 1/2/3 redundant rounds generate AES-256 throughput of 5.3/4.98/4.7 Gb/s, incurring a performance overhead of 13%/18%/23% compared to an unprotected AES. Undervoltage attack measurements show fault coverage of 99.98%, representing a <inline-formula> <tex-math>$5000{times }$ </tex-math></inline-formula> MTD improvement. Random additive-masking circuits with redundant composite-field computations demonstrate a measured MTD of >1 billion encryption traces.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1349-1358"},"PeriodicalIF":4.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143518733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process 用于5纳米FinFET工艺PAM-4光直接检测的8通道800 gb /s收发器

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-02-27 DOI: 10.1109/JSSC.2025.3541174

Fabio Giunco;Marco Sosio;Claudio Nani;Ivan Fabiano;Travis Lovitt;Victor Karam;Domenico Albano;Claudio Asero;Nicola Codega;Marco Garampazzi;Nicola Ghittori;Leonardo Daniel Herbas Burgos;Stanley S. K. Ho;Enrico Monaco;B. Reyes;P. Rossi;Enrico Temporiti;Paolo Pascale;Fernando De Bernardinis;Shawn Scouten;Stephen Jantzi

{"title":"An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process","authors":"Fabio Giunco;Marco Sosio;Claudio Nani;Ivan Fabiano;Travis Lovitt;Victor Karam;Domenico Albano;Claudio Asero;Nicola Codega;Marco Garampazzi;Nicola Ghittori;Leonardo Daniel Herbas Burgos;Stanley S. K. Ho;Enrico Monaco;B. Reyes;P. Rossi;Enrico Temporiti;Paolo Pascale;Fernando De Bernardinis;Shawn Scouten;Stephen Jantzi","doi":"10.1109/JSSC.2025.3541174","DOIUrl":"10.1109/JSSC.2025.3541174","url":null,"abstract":"In this article, we present an eight-lane 800-Gb/s transceiver, which enables the implementation of pluggable optical modules with pulse amplitude modulation (PAM)-4 modulation and direct detection. The transceiver features a host interface composed of eight TX and RX lanes compliant with the optical internetworking forum (OIF) common electrical I/O (CEI) 112G very short reach (VSR) and IEEE 802.3 chip to module (C2M) standards and integrates eight TX and RX lanes on the optical (line) side. Three fully integrated high-voltage optical TXs have been integrated with minimum area and power overhead by changing only few top metal masks: 3-Vpp silicon photonics (SiPho), 3-V open drain (OD), and 1.5-Vpp electro absorption modulated laser (EML) driver. External additional drivers suitable, e.g., for vertical cavity surface emitting laser (VCSEL) applications are supported by exploiting optical driver software reconfigurability into standard driver mode. The optical RXs, identical for all the applications, are digital signal processing (DSP) based, with the analog section consisting of a variable gain amplifier (VGA) and an analog-to-digital converter (ADC). The VGA can be dc coupled to an external trans-impedance amplifier (TIA) without the need for external components. The chip is implemented in 5-nm FinFET technology and it is designed to deliver the target performance both in package and bare die. Both versions meet the form factor and power requirements for quad small form factor pluggable double density (QSFP-DD) multi-source agreement (MSA) specifications and are suitable for optical interconnects covering most of the optical standards such as DR8/2xFR4/LR8/SR8.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1277-1288"},"PeriodicalIF":4.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143518729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current 电感电流减小的双电感四路混合降压（2L4PHB）转换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-02-27 DOI: 10.1109/jssc.2025.3543582

Wen-Liang Zeng, Guigang Cai, Yan Lu, Sai-Weng Sin, Rui P. Martins, Chi-Seng Lam

引用次数: 0

An Emulated Curve Assisted Fast-Transient Buck Converter With One-Cycle Charge Balance 一种模拟曲线辅助的单周期电荷平衡快速瞬态降压变换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-02-25 DOI: 10.1109/jssc.2025.3539593

Zihao Tang, Yan Lu, Rui P. Martins, Mo Huang

引用次数: 0

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