IEEE Journal of Solid-state Circuits最新文献

{"title":"A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics","authors":"Qiankai Cao;Juin Chuen Oh;Jie Gu","doi":"10.1109/JSSC.2025.3541484","DOIUrl":"10.1109/JSSC.2025.3541484","url":null,"abstract":"This work presents a footstep planning chip for humanoid robot. It integrates a time-domain graph search engine for high-level 3-D footstep planning and a mixed-signal zero moment point (ZMP) gait scheduler with neural inverse kinematics, enabling efficient low-level motion control. The key contributions of this work include a time-domain graph search engine for 3-D footstep planning, featuring 3-D search capabilities, <inline-formula> <tex-math>$D^{ast } $ </tex-math></inline-formula> replanning for real-time adjustments, redundant path blocking, and efficient result readout. In addition, it introduces an energy-efficient mixed-signal ZMP gait scheduler for maintaining robot balance, along with a time-domain neural-network-based inverse kinematics module for controlling robot joints. This work is demonstrated in situ on a fully assembled robot using the 65-nm system-on-chip (SoC), achieving <inline-formula> <tex-math>$2.7times $ </tex-math></inline-formula> energy savings for graph search and an <inline-formula> <tex-math>$18.4times $ </tex-math></inline-formula> improvement in energy efficiency for motion control compared with prior works.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1339-1348"},"PeriodicalIF":4.6,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143451730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2.5–5-V Input 100-V Output 86.2% Peak Efficiency Fibonacci–Dickson Hybrid Converter for Acoustic Surface Audio Driver","authors":"Yifan Jiang, Yan Lu, Chen Hu, Junmin Jiang","doi":"10.1109/jssc.2025.3541341","DOIUrl":"https://doi.org/10.1109/jssc.2025.3541341","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"24 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143451731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PWM-Based Impedance Boosting Technique With Autonomous Background Calibration for VCO-Based Neural Front Ends","authors":"Huaiyu Liu, Yang Lin, Pujia Xing, Guoxing Wang, Yan Liu","doi":"10.1109/jssc.2025.3539843","DOIUrl":"https://doi.org/10.1109/jssc.2025.3539843","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"13 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143443629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a Compact Low-Power Sub-2.4-GHz Transceiver for Medical Band Applications","authors":"Heng Huang;Xiliang Liu;Zijian Tang;Wei Song;Yuan Ma;Yuwei Zhang;Xiaoyan Ma;Milin Zhang;Jintao Wang;Kai Lu;Zhihua Wang;Guolin Li","doi":"10.1109/JSSC.2024.3519534","DOIUrl":"10.1109/JSSC.2024.3519534","url":null,"abstract":"This article proposes a compact low-power sub-2.4-GHz transceiver (TRX) with a all-digital phase-locked loop (ADPLL)-based transmitter (TX) and a single-path phase-tracking receiver (RX) in a 40-nm CMOS process. To meet the requirements for low output power in the medical band as well as to reduce power consumption, a single-ended class-E power amplifier (PA) with a duty-cycle-controlled strategy is proposed. A fully integrated on-chip matching network is designed to satisfy the impedance matching criteria for the class-E PA. The issues of the 2nd-order and the 3rd-order harmonic suppression are resolved by a series resonator and a capacitor in parallel with a segmented transformer, respectively. In the RX, the on-chip transformer also serves as an input impedance matching network for the low-noise transconductance amplifier (LNTA), reducing the required transconductance through passive reverse voltage gain. The transformer is capable of suppressing noise. The structure of the matching network only requires one transformer and one inductor, thereby reducing the count of passive components. Additionally, it features an embedded transmitter/receiver (T/R) switch function without insertion loss. The proposed 8-port transformer makes the layout more flexible and compact. The TX consumes 2.27 mW at −10-dBm output power and 5.45 mW at 0 dBm. A 2nd-order harmonic distortion of −52.36 dBm and a 3rd-order harmonic distortion of −50.67 dBm are measured, respectively. The RX consumes 2.25 mW and achieves a sensitivity of −93 dBm. The proposed TRX with reused matching networks results in an active silicon area of only 0.48 mm2.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1516-1528"},"PeriodicalIF":4.6,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143417339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Column-Parallel On-Programming Pixel-Current Readout Embedded in an OLED Display Driver IC","authors":"Gyu-Wan Lim;Dong-Kyu Kim;Gyeong-Gu Kang;Seunghwa Shin;Kihyun Kim;Yousung Park;Won Kim;Young-Bok Kim;Hyun-Kyu Jeon;Hyun-Sik Kim","doi":"10.1109/JSSC.2025.3538075","DOIUrl":"10.1109/JSSC.2025.3538075","url":null,"abstract":"This article presents an organic light-emitting diode (OLED) driver IC that embeds a column-parallel real-time pixel-current readout circuit for sensing current during actual display operation. It features a folding integrator (FI) for high sensitivity and wide dynamic range (DR) in current sensing, along with a source-driven pixel and an AFE-combined voltage driver (ACD) to facilitate current sensing during display data programming. A channel-shared common-mode noise rejection filter (CMRF) is also presented to effectively suppress channel-common panel noise. The 16-channel prototype chip was fabricated using a 180-nm CMOS process. Measurement results show that the FI achieves 80-mV/nA sensitivity and a 16-fold DR extension, while the CMRF offers up to 63 dB of noise rejection. The 11-bit current readout exhibits a maximum differential nonlinearity (DNL) of 0.33 LSB, an integral nonlinearity (INL) of 1.7 LSB, an rms noise of 1.98 digital number (DN), and a signal-to-noise ratio (SNR) of 60.3 dB. Real demonstrations with LED also validate the pixel-current sensing functionality and performance of the proposed chip.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1174-1189"},"PeriodicalIF":4.6,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143417340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 94.7-dB Dynamic Range Fully Passive Switched-Capacitor Low-Pass Filter With Enhanced Selectivity","authors":"Farzan Rezaei, Loai G. Salem","doi":"10.1109/jssc.2025.3539170","DOIUrl":"https://doi.org/10.1109/jssc.2025.3539170","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"23 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143417351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI","authors":"Seongyon Hong;Wooyoung Jo;Sangjin Kim;Sangyeob Kim;Soyeon Um;Kyomin Sohn;Hoi-Jun Yoo","doi":"10.1109/JSSC.2025.3538899","DOIUrl":"10.1109/JSSC.2025.3538899","url":null,"abstract":"This article proposes Dyamond, a one transistor, one capacitor (1T1C) dynamic random access memory (DRAM) in-memory computing (IMC) accelerator with architecture-to-circuit-level optimizations for high memory density and energy efficiency. The bit column addition (BCA) dataflow introduces output bit-wise accumulation to exploit varying accuracy and energy characteristics across different bit positions. The lower BCA (LBCA) reduces analog-to-digital converter (ADC) operations to enhance energy efficiency with inter-column analog accumulation. The higher BCA (HBCA) improves accuracy through signal enhancement and minimizes energy consumption per ADC readout with signal shift (SS). The design maximizes memory density by dedicating 1T1C cells solely to memory and integrating a compact computation circuit adjacent to the bitline sense amplifier. The memory access power is further reduced with a big-little array structure and a switchable sense amplifier (SWSA), which trades off retention time and energy consumption. Fabricated in 28-nm CMOS, Dyamond integrates 3.54-MB DRAM in a 6.48-mm2 area, achieving 27.2 TOPS/W peak efficiency and outstanding performance in advanced models such as BERT and GPT-2.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1299-1310"},"PeriodicalIF":4.6,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143418364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.028-mm2 32-MHz RC Frequency Reference With an Inaccuracy of ±900 ppm From -40 ∘C to 125 ∘C and ±1600 ppm After Accelerated Aging","authors":"Sining Pan, Yihang Cheng, Guohua Wu, Zhihua Wang, Kofi A. A. Makinwa, Huaqiang Wu","doi":"10.1109/jssc.2025.3530944","DOIUrl":"https://doi.org/10.1109/jssc.2025.3530944","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"21 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143401941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2000-volumes/s 3-D Ultrasound Probe With Monolithically-Integrated 23 × 23-mm² 4096 -Element CMUT Array","authors":"Nuriel N. M. Rozsa;Zhao Chen;Taehoon Kim;Peng Guo;Yannick M. Hopf;Jason Voorneveld;Djalma Simoes dos Santos;Emile Noothout;Zu-Yao Chang;Chao Chen;Vincent A. Henneken;Nico de Jong;Hendrik J. Vos;Johan G. Bosch;Martin D. Verweij;Michiel A. P. Pertijs","doi":"10.1109/JSSC.2025.3534087","DOIUrl":"10.1109/JSSC.2025.3534087","url":null,"abstract":"This article presents a 4096-element ultrasound probe for high volume-rate (HVR) cardiovascular imaging. The probe consists of two application-specific integrated circuits (ASICs), each of which interfaces with a 2048-element monolithically-integrated capacitive micro-machined ultrasound transducer (CMUT) array. The probe can image a <inline-formula> <tex-math>$60{^{circ }} times 60{^{circ }} times 10$ </tex-math></inline-formula>-cm volume at 2000 volumes/s, the highest volume-rate with in-probe channel-count reduction reported to date. It uses <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> delay-and-sum micro-beamforming (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>BF) and <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> time-division multiplexing (TDM) to achieve an <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> receive (RX) channel-count reduction. Equalization, trained using a pseudorandom bit-sequence generated on the chip, reduces TDM-induced crosstalk by 10 dB, enabling power-efficient scaling of the cable drivers. The ASICs also implement a novel transmit (TX) beamformer (BF) that operates as a programmable digital pipeline, which enables steering of arbitrary pulse-density modulated (PDM) waveforms. The TX BF drives element-level 65 V unipolar pulsers, which in turn drive the CMUT array. Both the TX BF and RX <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>BF are programmed with shift-registers (SRs) that can either be programmed in a row-column fashion for fast upload times, or daisy-chain fashion for a higher flexibility. The layout of the ASICs is matched to the 365-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-pitch monolithically-integrated CMUT array. While operating, the RX and logic power consumption per element is 0.85 and 0.10 mW, respectively. TX power consumption is highly waveform dependent, but is nominally 0.34 mW. Compared to the prior art, the probe has the highest volume rate, and features among the largest imaging arrays (both in terms of element-count and aperture) with a high flexibility in defining the TX waveform. These properties make it a suitable option for applications requiring HVR imaging of a large region of interest.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1397-1410"},"PeriodicalIF":4.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143392973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier","authors":"Kyeongtae Nam;Dongil Lee;Kyuchang Kang;Sang-Yun Kim;Changyoung Lee;Hyunchul Yoon;Donggeon Kim;Bokyeon Won;Jae-Joon Song;Jaehyuk Kim;Incheol Nam;Young-Hun Seo;Jeong-Don Ihm;Changsik Yoo;Sangjoon Hwang","doi":"10.1109/JSSC.2025.3531904","DOIUrl":"10.1109/JSSC.2025.3531904","url":null,"abstract":"A bitline sense amplifier (BLSA) with offset compensated charge transfer pre-sensing (OC-CTPS) scheme is implemented using 14-nm dynamic random access memory (DRAM) process. The offset compensation (OC) is operated by diode connection without additional size overhead for BLSA. The average fail bit count (FBC) attributed to a mismatch of charge transfer (CT) transistor was reduced by 94% after performing OC. Furthermore, the proposed OC-CTPS BLSA accomplished 250 and 500 ps of CT time (<inline-formula> <tex-math>$t_{mathrm {CT}}$ </tex-math></inline-formula>) window, representing the <inline-formula> <tex-math>$t_{mathrm {CT}}$ </tex-math></inline-formula> region where the FBC is lower than the standard FBC, at the temperatures of <inline-formula> <tex-math>$- 25~^{circ }$ </tex-math></inline-formula>C and <inline-formula> <tex-math>$100~^{circ }$ </tex-math></inline-formula>C, respectively, without modifying any operations for CT. Moreover, our approach ensures robust and stable sensing even at operating voltages as low as 0.75 V, compared to conventional latch-based OC BLSA.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1359-1367"},"PeriodicalIF":4.6,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143385770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}