IEEE Journal of Solid-state Circuits最新文献_第9页

A 94.4% Peak Efficiency Coupled-Inductor Hybrid Step-Up Converter With Load-Independent Output Voltage Ripple 峰值效率为 94.4%、输出电压纹波与负载无关的耦合电感器混合升压转换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510392

Peng Cao, Danzhu Lu, Jiawei Xu, Zhiliang Hong

引用次数: 0

An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA 基于电流复用的低功率LNA电感负载同步噪声与输入匹配技术

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3511578

Phuoc B. T. Huynh, Gyeong-Seok Lee, Jun-Young Park, Tae-Yeoul Yun

引用次数: 0

A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC 一个2.72 fj /转换步长13位SAR ADC，具有宽共模互补分裂前置放大器比较器和接地手指CDAC

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510883

Sewon Lee, Hyein Kang, Minjae Lee

引用次数: 0

Pseudo Hysteretic Controlled Gap Time Modulated Isolated DC–DC Converter With Common-Mode Transient Immunity 具有共模暂态抗扰度的伪滞后控制间隙时间调制隔离型DC-DC变换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510362

Yang Liu, Yuan Yao, Lin Cheng, Wing-Hung Ki

引用次数: 0

Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing 基于 FHE 的隐私保护计算的高能效灵活 RNS-CKKS 处理器

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/JSSC.2024.3510917

Hyeokjun Kwon;Hyunhoon Lee;Gyuhyun Jung;Youngjoo Lee

{"title":"Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing","authors":"Hyeokjun Kwon;Hyunhoon Lee;Gyuhyun Jung;Youngjoo Lee","doi":"10.1109/JSSC.2024.3510917","DOIUrl":"10.1109/JSSC.2024.3510917","url":null,"abstract":"This article proposes a total hardware solution for the RNS-CKKS algorithm supporting flexible parameter sets with 2.7-to-13.3-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>J/boot/slot energy consumption. Targeting fully homomorphic encryption (FHE), we focus on the key-switch operation, which is the most essential, complicated operation for the bootstrapping process to alleviate accumulated error and enable unlimited FHE computations. Introducing novel two-level scheduling schemes for low-latency key-switch operation, the proposed hardware reduces key-switch latency by 47% and increases resource utilization by <inline-formula> <tex-math>$1.9times $ </tex-math></inline-formula> compared with a straightforward process. Moreover, with optimized hardware engines dynamically supporting various ciphertext parameter sets, the proposed hardware fabricated in 28-nm CMOS technology enables the most efficient FHE operations with various bit-security levels than conventional hardware, especially <inline-formula> <tex-math>$4.3times $ </tex-math></inline-formula> better bootstrapping energy efficiency than state-of-the-art hardware.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"136-145"},"PeriodicalIF":4.6,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142805220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Quantum Controller IC With DRAG Generation in 40-nm Cryo-CMOS for Scalable Superconducting Quantum Computing 用于可扩展超导量子计算的40纳米Cryo-CMOS拖曳产生量子控制器IC

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510032

Kiseo Kang, Seongchan Bae, Donggyu Minn, Jaeho Lee, Jae-Yoon Sim

引用次数: 0

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS 一种用于28纳米CMOS存储器接口的64 Gb/s/引脚单端PAM-4发送器及其合并预强调电容峰值串扰消除方案

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-09 DOI: 10.1109/JSSC.2024.3509417

Weitao Wu;Hongzhi Wu;Liping Zhong;Xuxu Cheng;Xiongshi Luo;Dongfan Xu;Catherine Wang;Zhenghao Li;Quan Pan

{"title":"A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS","authors":"Weitao Wu;Hongzhi Wu;Liping Zhong;Xuxu Cheng;Xiongshi Luo;Dongfan Xu;Catherine Wang;Zhenghao Li;Quan Pan","doi":"10.1109/JSSC.2024.3509417","DOIUrl":"10.1109/JSSC.2024.3509417","url":null,"abstract":"A 64 Gb/s/pin single-ended four-level pulse amplitude modulation (PAM-4) transmitter (TX) incorporating a merged preemphasis capacitive-peaking (C-peaking) crosstalk cancellation (XTC) scheme and a 3-tap reconfigurable fractional-spaced feed-forward equalizer (FS-FFE) is presented. The proposed XTC scheme mitigates the far-end crosstalk (FEXT) without attenuating the output swing while maintaining high TX’s bandwidth. The proposed FS-FFE provides a compensation range beyond Nyquist frequency, thereby reducing the switching jitter (SWJ) and extending the widths of PAM-4 eyes. The reconfigurable feed-forward equalizer (FFE) tap assignment scheme enables the TX to operate in a wider range of scenarios without additional power consumption. Besides, the FFE) coefficient selector in the predriver eliminates the need for additional driver cells typically required by FFE taps, reducing parasitic capacitance at the TX output and further improving the TX bandwidth by 60%. The measurement results show that the TX achieves an energy efficiency of 1.27 pJ/bit at 64 Gb/s with a total insertion loss of −11 dB and FEXT of −15.8 dB at 16 GHz. The proposed merged C-peaking XTC scheme decreases the crosstalk-induced jitter (CIJ) ratio by 82%.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"205-216"},"PeriodicalIF":4.6,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142797241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics 蜂群机器人基于位置共享的65nm 17.96 tops /W多智能体神经形态SLAM加速器BEE-SLAM

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-09 DOI: 10.1109/jssc.2024.3505960

Jaehyun Lee, Dong-Gu Choi, Gain Kim, Minyoung Song, Jong-Hyeok Yoon

引用次数: 0

Design and Implementation of a D-Band Bidirectional Common-Gate Amplifier in 45-nm RFSOI 45纳米RFSOI中d波段双向共门放大器的设计与实现

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-09 DOI: 10.1109/jssc.2024.3504358

Syed Mohammad Ashab Uddin, Wooram Lee

引用次数: 0

A Compact 180-GHz Stacked-FET Oscillator With 11-dBm Output Power and 13.9% DC-to-RF Efficiency in a 45-nm CMOS SOI Process 一种紧凑的180 ghz堆叠fet振荡器，输出功率为11 dbm， dc - rf效率为13.9%，采用45纳米CMOS SOI工艺