IEEE Journal of Solid-state Circuits最新文献_第9页

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture 一种3nm - finfet 4.3 GHz 21.1 Mb/mm双泵浦1读1写伪2端口SRAM，具有折叠位线多银行架构

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-12 DOI: 10.1109/JSSC.2024.3509958

Masaru Haraguchi;Yorinobu Fujino;Yoshisato Yokoyama;Ming-Hung Chang;Yu-Hao Hsu;Hong-Chen Cheng;Koji Nii;Yih Wang;Tsung-Yung Jonathan Chang

{"title":"A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture","authors":"Masaru Haraguchi;Yorinobu Fujino;Yoshisato Yokoyama;Ming-Hung Chang;Yu-Hao Hsu;Hong-Chen Cheng;Koji Nii;Yih Wang;Tsung-Yung Jonathan Chang","doi":"10.1109/JSSC.2024.3509958","DOIUrl":"10.1109/JSSC.2024.3509958","url":null,"abstract":"A double-pumped 1-read and 1-write pseudo-2-port 6T static random access memory (SRAM) with folded bitline (BL) multi-bank (MB) architecture is demonstrated on 3 nm FinFET technology. A new self-timed clock generator is proposed to optimize wordline (WL) negating with shortcut path circuit (WLNS). sense-amplifier-enable interlocking (SAEI) circuit and the clock generator can provide a 3.6% increase in the maximum operating frequency (<inline-formula> <tex-math>$f_{text {MAX}}$ </tex-math></inline-formula>) by minimizing the tail period of the read operation. The data pre-loading write driver (PLWD) circuit facilitates a shorter separation time between read and write operations by overlapping BL pre-charge and write data loading on the BL, thereby leading to a 4.4% improvement in <inline-formula> <tex-math>$f_{text {MAX}}$ </tex-math></inline-formula>. The WLNS and PLWD contribute to 2.4% <inline-formula> <tex-math>$f_{text {MAX}}$ </tex-math></inline-formula> gain by promoting contention-free features between the BL pre-charge and write driver circuits. Furthermore, the real-time dynamic performance scaling (RTDPS) feature ensures a robust SRAM read/write operation across the entire supply voltage range by optimizing WL pulsewidth. The test chip measurement results show that it achieves a 5.9% increase in <inline-formula> <tex-math>$f_{text {MAX}}$ </tex-math></inline-formula> at high voltage ranges. In addition, the memory density is 21.1 Mb/mm2, and <inline-formula> <tex-math>$f_{text {MAX}}$ </tex-math></inline-formula> is 4.3 GHz, resulting in a figure of merit (FoM) of 90.7 GHz <inline-formula> <tex-math>$times $ </tex-math></inline-formula> Mb/mm2/V.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"197-204"},"PeriodicalIF":4.6,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142815720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Class-G Impedance-Modulation Multi-Core Power Oscillator for High $P_{text{out}}$ and Power Back-Off Efficiency Enhancement 用于高P_{text{out}}$和增强功率回退效率的g类阻抗调制多核功率振荡器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-12 DOI: 10.1109/jssc.2024.3510417

Yiyang Shu, Xun Luo

引用次数: 0

A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75-$mu$s Conversion Time and 0.4-mm2 Active Area 一种用于无刷直流电机控制的78.2 db动态范围分流电流传感器，转换时间为2.75-$mu$s，有效面积为0.4 mm2

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510926

Antonio Aprile, Jaya Satyanarayana Yarragunta, Andreas Fugger, Francesco Conzatti, Edoardo Bonizzoni, Piero Malcovati

引用次数: 0

A 94.4% Peak Efficiency Coupled-Inductor Hybrid Step-Up Converter With Load-Independent Output Voltage Ripple 峰值效率为 94.4%、输出电压纹波与负载无关的耦合电感器混合升压转换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510392

Peng Cao, Danzhu Lu, Jiawei Xu, Zhiliang Hong

引用次数: 0

An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA 基于电流复用的低功率LNA电感负载同步噪声与输入匹配技术

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3511578

Phuoc B. T. Huynh, Gyeong-Seok Lee, Jun-Young Park, Tae-Yeoul Yun

引用次数: 0

A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC 一个2.72 fj /转换步长13位SAR ADC，具有宽共模互补分裂前置放大器比较器和接地手指CDAC

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510883

Sewon Lee, Hyein Kang, Minjae Lee

引用次数: 0

Pseudo Hysteretic Controlled Gap Time Modulated Isolated DC–DC Converter With Common-Mode Transient Immunity 具有共模暂态抗扰度的伪滞后控制间隙时间调制隔离型DC-DC变换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510362

Yang Liu, Yuan Yao, Lin Cheng, Wing-Hung Ki

引用次数: 0

Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing 基于 FHE 的隐私保护计算的高能效灵活 RNS-CKKS 处理器

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/JSSC.2024.3510917

Hyeokjun Kwon;Hyunhoon Lee;Gyuhyun Jung;Youngjoo Lee

{"title":"Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing","authors":"Hyeokjun Kwon;Hyunhoon Lee;Gyuhyun Jung;Youngjoo Lee","doi":"10.1109/JSSC.2024.3510917","DOIUrl":"10.1109/JSSC.2024.3510917","url":null,"abstract":"This article proposes a total hardware solution for the RNS-CKKS algorithm supporting flexible parameter sets with 2.7-to-13.3-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>J/boot/slot energy consumption. Targeting fully homomorphic encryption (FHE), we focus on the key-switch operation, which is the most essential, complicated operation for the bootstrapping process to alleviate accumulated error and enable unlimited FHE computations. Introducing novel two-level scheduling schemes for low-latency key-switch operation, the proposed hardware reduces key-switch latency by 47% and increases resource utilization by <inline-formula> <tex-math>$1.9times $ </tex-math></inline-formula> compared with a straightforward process. Moreover, with optimized hardware engines dynamically supporting various ciphertext parameter sets, the proposed hardware fabricated in 28-nm CMOS technology enables the most efficient FHE operations with various bit-security levels than conventional hardware, especially <inline-formula> <tex-math>$4.3times $ </tex-math></inline-formula> better bootstrapping energy efficiency than state-of-the-art hardware.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"136-145"},"PeriodicalIF":4.6,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142805220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Quantum Controller IC With DRAG Generation in 40-nm Cryo-CMOS for Scalable Superconducting Quantum Computing 用于可扩展超导量子计算的40纳米Cryo-CMOS拖曳产生量子控制器IC

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI: 10.1109/jssc.2024.3510032

Kiseo Kang, Seongchan Bae, Donggyu Minn, Jaeho Lee, Jae-Yoon Sim

引用次数: 0

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS 一种用于28纳米CMOS存储器接口的64 Gb/s/引脚单端PAM-4发送器及其合并预强调电容峰值串扰消除方案

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-12-09 DOI: 10.1109/JSSC.2024.3509417

Weitao Wu;Hongzhi Wu;Liping Zhong;Xuxu Cheng;Xiongshi Luo;Dongfan Xu;Catherine Wang;Zhenghao Li;Quan Pan

{"title":"A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS","authors":"Weitao Wu;Hongzhi Wu;Liping Zhong;Xuxu Cheng;Xiongshi Luo;Dongfan Xu;Catherine Wang;Zhenghao Li;Quan Pan","doi":"10.1109/JSSC.2024.3509417","DOIUrl":"10.1109/JSSC.2024.3509417","url":null,"abstract":"A 64 Gb/s/pin single-ended four-level pulse amplitude modulation (PAM-4) transmitter (TX) incorporating a merged preemphasis capacitive-peaking (C-peaking) crosstalk cancellation (XTC) scheme and a 3-tap reconfigurable fractional-spaced feed-forward equalizer (FS-FFE) is presented. The proposed XTC scheme mitigates the far-end crosstalk (FEXT) without attenuating the output swing while maintaining high TX’s bandwidth. The proposed FS-FFE provides a compensation range beyond Nyquist frequency, thereby reducing the switching jitter (SWJ) and extending the widths of PAM-4 eyes. The reconfigurable feed-forward equalizer (FFE) tap assignment scheme enables the TX to operate in a wider range of scenarios without additional power consumption. Besides, the FFE) coefficient selector in the predriver eliminates the need for additional driver cells typically required by FFE taps, reducing parasitic capacitance at the TX output and further improving the TX bandwidth by 60%. The measurement results show that the TX achieves an energy efficiency of 1.27 pJ/bit at 64 Gb/s with a total insertion loss of −11 dB and FEXT of −15.8 dB at 16 GHz. The proposed merged C-peaking XTC scheme decreases the crosstalk-induced jitter (CIJ) ratio by 82%.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 1","pages":"205-216"},"PeriodicalIF":4.6,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142797241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0