IEEE Journal of Solid-state Circuits最新文献

{"title":"A 50-MHz Pulse-Width Modulator Embodying Low-Loss Quasi-Dynamic Comparators for Very High-Frequency DC–DC Converters","authors":"Sun-Yang Tay, Victor Adrian, Joseph S. Chang","doi":"10.1109/jssc.2025.3562008","DOIUrl":"https://doi.org/10.1109/jssc.2025.3562008","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"8 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143915405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Highly Power-Efficient Input-Boosted First Stage for Capacitively Coupled Chopper Instrumentation Amplifiers","authors":"Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Linxiao Shen","doi":"10.1109/jssc.2025.3564316","DOIUrl":"https://doi.org/10.1109/jssc.2025.3564316","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"5 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143915403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4-Ch × 64 Gb/s/Ch NRZ VCSEL-Based Co-Packaged Fiber-Terminated Optical TX and 80-Gb/s Optical Driver","authors":"Susnata Mondal, Junyi Qiu, Sashank Krishnamurthy, Joseph Kennedy, Soumya Bose, Tolga Acikalin, Shuhei Yamada, James Jaussi, Mozhgan Mansuri","doi":"10.1109/jssc.2025.3563073","DOIUrl":"https://doi.org/10.1109/jssc.2025.3563073","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"68 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143898347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 200-GHz Modulable Transceiver With 35-dB Tx On–Off Isolation and 16-Gb/s Code Rate for MIMO Radar in 130-nm SiGe Process","authors":"Rui Zhou, Jixin Chen, Si-Yuan Tang, Zekun Li, Dawei Tang, Bangjie Zhang, Feng Xie, Peigen Zhou, Yan Huang, Gang Xu, Zhe Chen, Wei Hong","doi":"10.1109/jssc.2025.3563825","DOIUrl":"https://doi.org/10.1109/jssc.2025.3563825","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"114 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143898339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaged K-/Ka-Band Down/Up Frequency Converter Chipsets for Phased Array SATCOM Ground Terminals in 65-nm CMOS","authors":"Peng Gu, Enqi Zheng, Chenyu Xu, Huiqi Liu, Dixian Zhao","doi":"10.1109/jssc.2025.3563511","DOIUrl":"https://doi.org/10.1109/jssc.2025.3563511","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"18 1","pages":"1-15"},"PeriodicalIF":5.4,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143893618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels","authors":"Nader Sherif Kassem Fathy, Ritwik Vatsyayan, Andrew M. Bourhis, Shadi A. Dayeh, Patrick P. Mercier","doi":"10.1109/jssc.2025.3560316","DOIUrl":"https://doi.org/10.1109/jssc.2025.3560316","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"93 1","pages":"1-13"},"PeriodicalIF":5.4,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143893621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS","authors":"Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh","doi":"10.1109/jssc.2025.3562885","DOIUrl":"https://doi.org/10.1109/jssc.2025.3562885","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"20 1","pages":"1-11"},"PeriodicalIF":5.4,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143893624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core","authors":"Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Gwangtae Park, Sangyeob Kim, Soyeon Kim, Donghyeon Han, Hoi-Jun Yoo","doi":"10.1109/jssc.2025.3562515","DOIUrl":"https://doi.org/10.1109/jssc.2025.3562515","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"72 1","pages":"1-13"},"PeriodicalIF":5.4,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143893620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AIA: A Customized Multi-Core RISC-V SoC for Discrete Sampling Workloads in 16 nm","authors":"Shirui Zhao;Nimish Shah;Wannes Meert;Marian Verhelst","doi":"10.1109/JSSC.2025.3561880","DOIUrl":"10.1109/JSSC.2025.3561880","url":null,"abstract":"Probabilistic models (PMs) are essential in advancing machine learning capabilities, particularly in safety-critical applications involving reasoning and decision-making. Among the methods employed for inference in these models, sampling-based Markov chain Monte Carlo (MCMC) techniques are widely used. However, MCMC methods come with significant computational costs and are inherently challenging to parallelize, resulting in inefficient execution on conventional CPU/GPU platforms. To overcome these challenges, this article presents an approximate inference accelerator (AIA), a multi-core RISC-V system-on-chip (SoC) design fabricated using Intel’s 16 nm process technology. Our AIA is specifically designed to empower edge devices with robust decision-making and reasoning abilities. The AIA architecture incorporates an RISC-V host processor to manage chip-to-chip data communication and a 2-D mesh of 16 custom versatile RISC-V cores optimized for high-efficiency approximate inference. Each core features: 1) custom instructions and datapath blocks for non-normalized Knuth-Yao (KY) sampling, as well as for the interpolation of non-linear functions (e.g., logarithmic and exponential), and 2) direct data-access to the register file (RF) of each neighboring core, to reduce the data movement costs of frequent data exchanges between nearby cores. To further capitalize on the parallelism potential in MCMC algorithms, we developed a specialized compile chain that enables efficient spatial mapping and scheduling across the cores. As a result, AIA attains a peak sampling rate of 1277 MSamples/s at 0.9 V and achieves an energy efficiency of 20 GSamples/s/W at 0.7 V, surpassing the previous state-of-the-art (SotA) ASIC accelerator for probabilistic inference by up to <inline-formula> <tex-math>$6times $ </tex-math></inline-formula> in speed and <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> in energy efficiency. Furthermore, the AIA’s versatility is demonstrated through the successful mapping of different types of PM workloads onto the chip.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2447-2460"},"PeriodicalIF":4.6,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143893619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully Integrated Optical Injection Locking With Schottky Photodiodes in 65-nm CMOS","authors":"Arnaud Van Mieghem;Michiel Steyaert;Filip Tavernier","doi":"10.1109/JSSC.2025.3561578","DOIUrl":"10.1109/JSSC.2025.3561578","url":null,"abstract":"This article presents an optical injection-locked oscillator implemented in a standard 65-nm CMOS process with integrated Schottky photodiodes (PDs). This optoelectronic integration aims to facilitate synchronization and clock transmission in long-distance communication systems. The locking performance of N-well, P-well, and P-substrate Schottky PDs is compared using a CMOS cross-coupled LC oscillator for 1310- and 1550-nm light. The P-substrate diode demonstrated superior performance, reducing the free-running rms jitter from 38.7 to 1.02 ps at 1310 nm with 3.5-mW optical power or to 2.51 ps at 1550 nm with 1.0-mW optical power. Across three samples, the oscillator exhibited a tuning range from 2.9 to 3.3 GHz, with a maximum variance of 37 MHz and a power consumption of 4.41 mW. These findings underscore the potential of fully integrated optical systems in standard CMOS to enhance long-distance communication networks.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2384-2393"},"PeriodicalIF":4.6,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143890078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}