发布求助
文献互助 智能选刊 最新文献

IEEE Journal of Solid-state Circuits最新文献

筛选
英文 中文
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver CMOS 49 - 63 ghz锁相步进啁啾FMCW雷达收发器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-11 DOI: 10.1109/jssc.2025.3556649
Xuyang Liu, Md. Hedayatullah Maktoomi, Mahdi Alesheikh, Payam Heydari, Hamidreza Aghasi
{"title":"A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver","authors":"Xuyang Liu, Md. Hedayatullah Maktoomi, Mahdi Alesheikh, Payam Heydari, Hamidreza Aghasi","doi":"10.1109/jssc.2025.3556649","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556649","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"16 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS 一种40nm CMOS分段补偿56 gb /s PAM-4 VCSEL发射机
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3552590
Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue
{"title":"A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS","authors":"Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue","doi":"10.1109/jssc.2025.3552590","DOIUrl":"https://doi.org/10.1109/jssc.2025.3552590","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"183 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.00175 mm2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm 空间分辨率为35 μm的神经探针直接数字化前端：每通道0.00175 mm2和9.62 μW
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3555007
Roman Willaredt, Christoph Grandauer, Daniel De Dorigo, Matthias Kuhl, Yiannos Manoli
{"title":"A 0.00175 mm2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm","authors":"Roman Willaredt, Christoph Grandauer, Daniel De Dorigo, Matthias Kuhl, Yiannos Manoli","doi":"10.1109/jssc.2025.3555007","DOIUrl":"https://doi.org/10.1109/jssc.2025.3555007","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"25 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS 在 28-nm CMOS 中实现占空比开关 30-Gb/s 突发模式 CDR，锁定时间为 1.6-ns
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556524
Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs
{"title":"A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS","authors":"Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs","doi":"10.1109/jssc.2025.3556524","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556524","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"74 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction 基于粘合剂贴片机的可重构多传感器贴片接口，具有片上量化时域特征提取功能
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-10 DOI: 10.1109/jssc.2025.3556441
You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim
{"title":"An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction","authors":"You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim","doi":"10.1109/jssc.2025.3556441","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556441","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"105 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143819586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS 基于抖动滤波时钟和误码率优化技术的122gb /s PAM-4重定时器收发器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3555383
Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
{"title":"A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS","authors":"Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu","doi":"10.1109/jssc.2025.3555383","DOIUrl":"https://doi.org/10.1109/jssc.2025.3555383","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"442 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory 基于IGZO tft的6T1C突触记忆模拟神经形态片上训练系统
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3556123
Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee
{"title":"An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory","authors":"Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee","doi":"10.1109/jssc.2025.3556123","DOIUrl":"https://doi.org/10.1109/jssc.2025.3556123","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"24 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping 用于多方案读取映射的28纳米239bp /μJ敏捷泛基因组分析加速器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-08 DOI: 10.1109/jssc.2025.3554616
Yichi Zhang, Jianfeng Zhu, Liangwei Li, Gang Zeng, Dibei Chen, Tairan Zhang, Yeyang Deng, Zhicheng Gong, Aoyang Zhang, Yang Liu, Shaojun Wei, Leibo Liu
{"title":"A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping","authors":"Yichi Zhang, Jianfeng Zhu, Liangwei Li, Gang Zeng, Dibei Chen, Tairan Zhang, Yeyang Deng, Zhicheng Gong, Aoyang Zhang, Yang Liu, Shaojun Wei, Leibo Liu","doi":"10.1109/jssc.2025.3554616","DOIUrl":"https://doi.org/10.1109/jssc.2025.3554616","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"37 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143805689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision 一种8位精度的65nm数字随机内存计算CNN处理器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-07 DOI: 10.1109/jssc.2025.3554554
Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti
{"title":"A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision","authors":"Jiyue Yang, Tianmu Li, Wojciech Romaszkan, Puneet Gupta, Sudhakar Pamarti","doi":"10.1109/jssc.2025.3554554","DOIUrl":"https://doi.org/10.1109/jssc.2025.3554554","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"18 1","pages":""},"PeriodicalIF":5.4,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143797917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS 55纳米CMOS中基于多端口达灵顿单元的19- 45 GHz高效倍频器
IF 5.4 1区 工程技术
IEEE Journal of Solid-state Circuits Pub Date : 2025-04-04 DOI: 10.1109/jssc.2025.3553760
Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao, Kaixue Ma
{"title":"A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS","authors":"Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao, Kaixue Ma","doi":"10.1109/jssc.2025.3553760","DOIUrl":"https://doi.org/10.1109/jssc.2025.3553760","url":null,"abstract":"","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"108 1","pages":"1-16"},"PeriodicalIF":5.4,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143782435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信