一个紧凑的低抖动全数字分数输出分压器使用分裂- dtc为基础的背景校准

IF 5.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-08-29 DOI:10.1109/jssc.2025.3602127

Deng Luo, Yan Yu, Jianjun Chen, Yang Guo, Yaqing Chi, Guofang Yu, Hao Ding, Jing Xiao, Hao Gao, Ming Tao, Kai Tang, Bin Liang

引用次数: 0

摘要

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Compact Low-Jitter All-Digital Fractional Output Divider Using Split-DTC-Based Background Calibration

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.