具有背景反向跟踪DPD的周跳补偿FMCW数字锁相环

IF 5.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-07-30 DOI:10.1109/jssc.2025.3590136

Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Zhihua Wang, Baoyong Chi

引用次数: 0

摘要

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.