IEEE Transactions on Computers最新文献_第9页

TensorFHE+: Fully Homomorphic Encryption Acceleration Based on Linear Algebra TensorFHE+：基于线性代数的全同态加密加速

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-11-05 DOI: 10.1109/TC.2025.3629614

Yintai Sun;Shengyu Fan;Zhenhua Yin;Xinkai Song;Xing Hu;Zidong Du;Qi Guo;Weizhi Xu;Rui Hou;Dan Meng;Song Bian;Mingzhe Zhang

{"title":"TensorFHE+: Fully Homomorphic Encryption Acceleration Based on Linear Algebra","authors":"Yintai Sun;Shengyu Fan;Zhenhua Yin;Xinkai Song;Xing Hu;Zidong Du;Qi Guo;Weizhi Xu;Rui Hou;Dan Meng;Song Bian;Mingzhe Zhang","doi":"10.1109/TC.2025.3629614","DOIUrl":"https://doi.org/10.1109/TC.2025.3629614","url":null,"abstract":"Fully Homomorphic Encryption (FHE) enables encrypted data processing on untrusted cloud servers, crucial for privacy-sensitive applications. Despite its potential, performance overheads (about <inline-formula><tex-math>$10,000times$</tex-math></inline-formula> slower) limit adoption. ASIC accelerators outperform GPUs/FPGAs by optimizing specific operations but rely on costly 7nm processes and large on-chip memory, hindering cost-effective deployment. Balancing efficiency with manufacturing constraints remains critical. This paper presents TensorFHE+, a GPU-optimized FHE acceleration framework leveraging Tensor Cores to accelerate Number Theoretic Transform (NTT) operations. Key innovations include: 1) Decomposing CKKS kernels into vector/matrix operations for hardware utilization; 2) Vectorized modulo arithmetic; 3) Data layout optimization for memory efficiency. Evaluated on NVIDIA A100, TensorFHE+ outperforms TensorFHE[1] by <inline-formula><tex-math>$1.44times$</tex-math></inline-formula> in average (up to <inline-formula><tex-math>$1.69times$</tex-math></inline-formula> on ResNet-20) and surpasses prior GPU implementations <xref>[2]</xref>, <xref>[3]</xref>. The design also demonstrates compatibility with commercial linear algebra accelerators, enabling efficient FHE deployment.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"612-627"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FIITED: Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems fitited：推荐系统训练中的细粒度嵌入维数优化

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-11-17 DOI: 10.1109/TC.2025.3625161

Qinyi Luo;Penghan Wang;Wei Zhang;Fan Lai;Jiachen Mao;Xiaohan Wei;Jun Song;Wei-Yu Tsai;Shuai Yang;Yuxi Hu;Xuehai Qian

{"title":"FIITED: Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems","authors":"Qinyi Luo;Penghan Wang;Wei Zhang;Fan Lai;Jiachen Mao;Xiaohan Wei;Jun Song;Wei-Yu Tsai;Shuai Yang;Yuxi Hu;Xuehai Qian","doi":"10.1109/TC.2025.3625161","DOIUrl":"https://doi.org/10.1109/TC.2025.3625161","url":null,"abstract":"Huge embedding tables in modern deep learning recommender models (DLRM) require prohibitively large memory during training and inference. This paper proposes FIITED, a system to automatically reduce the memory footprint via FIne-grained In-Training Embedding Dimension pruning. By leveraging the key insight that embedding vectors are not equally important, FIITED adaptively adjusts the dimension of each individual embedding vector during model training, assigning larger dimensions to more important embeddings while adapting to dynamic changes in data. We prioritize embedding dimensions with higher frequencies and gradients as more important. To enable efficient pruning of embeddings and their dimensions during model training, we propose an embedding storage system based on virtually-hashed physically-indexed hash tables. Experiments on two industry models and months of realistic datasets show that FIITED can reduce DLRM embedding size by more than 65% while preserving model quality, outperforming state-of-the-art in-training embedding pruning methods and increasing the reduction ratio by 1.3<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> to 1.67<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>. On public datasets, FIITED can reduce the size of embedding tables by 2.2<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> to 800<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> with negligible accuracy drop, achieving 1.05<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> to 12.5<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> improvement in reduction ratio compared to baselines while improving model throughput.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"448-461"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SLAM: Extending the Reach of Ising Machine Advantage SLAM：扩大伊辛机器优势的范围

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-11-06 DOI: 10.1109/TC.2025.3630119

Matthew X. Burns;Zahra Azad;Yongchao Liu;Tony Geng;Hui Wu;Michael C. Huang

{"title":"SLAM: Extending the Reach of Ising Machine Advantage","authors":"Matthew X. Burns;Zahra Azad;Yongchao Liu;Tony Geng;Hui Wu;Michael C. Huang","doi":"10.1109/TC.2025.3630119","DOIUrl":"https://doi.org/10.1109/TC.2025.3630119","url":null,"abstract":"Dynamics-based Ising machines (IMs) are a promising substrate for high-speed combinatorial optimization and sampling. For problems that fit within their fixed capacity, they provide orders-of-magnitude speedups over conventional software algorithms. Once a problem exceeds hardware capacity, somewhat surprisingly, they become practically useless: Previous works generally relegate them to isolated sub-solvers. As our analysis will show, this approach produces no clear time or energy benefits, losing any inherent advantage of hardware IMs. After analyzing the shortcomings of previous hybrid proposals, we introduce a better method to extend IM advantage beyond hardware capacity. We call it the <bold>Stepped <bold>Large-neighborhood <bold>Annealing <bold>Method (<bold>SLAM), which drastically improves performance on combinatorial benchmarks with minimal host-side computation. We also propose novel architectural support to implement <bold>SLAM with low data movement overheads. The resulting augmented IM continues to exploit dynamical systems-enabled parallelism and thus maintains order of magnitude time-to-solution and energy-to-solution advantages over CPU-based algorithms. As a side benefit, our approach also significantly reduces the impact of device variation on solution quality, another perennial issue for analog optimizers.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"628-641"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Framework for Quantum Circuit Optimization: Comparators as a Case Study 量子电路优化的框架：比较器作为案例研究

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-12-12 DOI: 10.1109/TC.2025.3642981

Francisco Orts;Rodrigo Gil-Merino

{"title":"A Framework for Quantum Circuit Optimization: Comparators as a Case Study","authors":"Francisco Orts;Rodrigo Gil-Merino","doi":"10.1109/TC.2025.3642981","DOIUrl":"https://doi.org/10.1109/TC.2025.3642981","url":null,"abstract":"Qubits are the minimum unit of information in quantum computing. As current quantum devices have a very limited number of available qubits, finding circuits that optimize their use is crucial for this computing paradigm. Optimizing the qubits needed to implement a quantum circuit is not trivial, as these circuits have important restrictions such as the impossibility of copying values or the requirement that the computation done in them must always be reversible. This paper presents a framework for optimizing circuits for quantum computing. The framework is able to obtain, given a quantum circuit, an equivalent one that is more efficient in terms of number of qubits. In particular, the framework has applicability in quantum circuits dedicated to arithmetic operations such as addition or multiplication. As a representative case study, it is applied to a reversible comparator circuit, obtaining a design that reduces the number of qubits and controlled gates compared to other reversible comparators reported in the recent literature. As part of the work, a public repository is included with the necessary code to simplify any other circuit.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"706-719"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11298437","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware Trojan Object Detection Based on Bidirectional Graph Neural Networks 基于双向图神经网络的硬件木马目标检测

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-12-12 DOI: 10.1109/TC.2025.3642575

Dong Cheng;Xuanwei Lin;Chen Dong;Ximeng Liu;Kun Guo;Yirui Huang

{"title":"Hardware Trojan Object Detection Based on Bidirectional Graph Neural Networks","authors":"Dong Cheng;Xuanwei Lin;Chen Dong;Ximeng Liu;Kun Guo;Yirui Huang","doi":"10.1109/TC.2025.3642575","DOIUrl":"https://doi.org/10.1109/TC.2025.3642575","url":null,"abstract":"The rapid growth of Internet of Things (IoT) devices has heightened hardware security concerns, particularly with the emergence of hardware Trojans (HTs) as malicious components in integrated circuits. These HTs pose significant threats to information privacy and system performance. The early detection methods rely on golden references and domain knowledge, limiting their implementation in large-scale integrated circuits. Traditional machine learning-based HT detections can effectively identify infected circuits without golden chips. However, locating and evaluating the specific behavior of HTs in vast and complex circuits is challenging. To address these challenges, this paper presents an HT Object Detection (HTOD) problem, which involves two primary tasks: identifying the boundaries and sizes of HTs within circuits and distinguishing between different HT behaviors. We have developed a two-stage HT object detection framework based on a bidirectional jumping knowledge network called HTOD-BGNN to solve the HTOD problem, which enables progressive refinement of localized regions. It incorporates enhanced base-type features to ensure scalability and information retention during modeling. Additionally, the implementation of sample augmentation alleviates the challenges of sample imbalance and scarcity. The proposed method enables more intelligent circuit detection, achieving 100% and 87.5% detection rates for Trojan triggering and payload behaviors, respectively. It demonstrates superior localization performance and effective generalization to unseen circuit scenarios via its region refinement mechanism, achieving F1-scores of 54.01% on TrustHub and 90.04% on TRIT datasets.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"665-679"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Configurable Hardware Acceleration for Hyperdimensional Computing Extension on RISC-V RISC-V上超维计算扩展的可配置硬件加速

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-12-10 DOI: 10.1109/TC.2025.3642250

Rocco Martino;Marco Angioli;Antonello Rosato;Marcello Barbirotta;Abdallah Cheikh;Mauro Olivieri

{"title":"Configurable Hardware Acceleration for Hyperdimensional Computing Extension on RISC-V","authors":"Rocco Martino;Marco Angioli;Antonello Rosato;Marcello Barbirotta;Abdallah Cheikh;Mauro Olivieri","doi":"10.1109/TC.2025.3642250","DOIUrl":"https://doi.org/10.1109/TC.2025.3642250","url":null,"abstract":"Hyperdimensional Computing (HDC) is a neuro-inspired computational model that represents and manipulates information using high-dimensional distributed representations that are combined and compared using simple and highly parallel vector operations. In this work, we present a highly flexible hardware acceleration unit for HDC learning tasks based on the binary spatter-code model. Integrated into the execution stage of the Klessydra-T03 RISC-V core, the unit accelerates the core arithmetic operations of HDC and can be configured at synthesis time in terms of hardware parallelism, supported operations, and size of the local memories, trading off execution time with hardware resources to match application needs. A custom RISC-V Instruction Set Extension efficiently controls the accelerator, with instructions fully integrated into the GNU Compiler Collection toolchain and exposed to the programmer as intrinsics. Dedicated Control and Status Registers allow specifying the characteristics of the high-dimensional space and the target learning tasks at runtime, controlling the hardware loops of the accelerator and enabling the same hardware architecture to be used for various tasks. The dual flexibility coming from hardware configuration and software programmability sets this work apart from application-specific solutions in the literature, offering a unique, versatile accelerator adaptable to a wide range of applications and learning tasks.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"653-664"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SEMU: Concurrency-Optimized High-Performance Cache Management for Key-Value Caches SEMU：键值缓存的并发优化高性能缓存管理

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-12-12 DOI: 10.1109/TC.2025.3643461

Xiaoliang Wang;Peiquan Jin;Yigui Yuan

{"title":"SEMU: Concurrency-Optimized High-Performance Cache Management for Key-Value Caches","authors":"Xiaoliang Wang;Peiquan Jin;Yigui Yuan","doi":"10.1109/TC.2025.3643461","DOIUrl":"https://doi.org/10.1109/TC.2025.3643461","url":null,"abstract":"Improving software-managed cache efficiency is an important issue for various modern applications. Although LRU (Least Recently Used) is widely used as the default replacement policy in many key-value caches, it suffers from poor concurrency performance due to frequent list updates. However, existing concurrency-aware schemes like FIFO sacrifice the LRU’s temporal locality of data access, leading to a drop in the cache’s hit ratio. In this work, aiming to improve the concurrency performance of cache management while maintaining a high hit ratio as LRU, we propose a novel concurrency-aware cache replacement policy called SEMU (SEgment-based MUlti-version cache replacement) that outperforms state-of-the-art schemes. The novelty of SEMU lies in two aspects. First, it uses an append-only segment-based FIFO list to avoid locking the list, yielding high concurrency performance. Second, it adopts a multi-version mechanism to make the cache aware of temporal locality in data access, which can achieve a high hit ratio similar to LRU. With such designs, SEMU can offer high concurrency and a high cache hit ratio. We conduct extensive experiments on both synthetic and real-world workloads to compare SEMU with a few existing schemes, including LRU, FIFO, 2Q, and FrozenHot. We also implement SEMU into a real key-value store, RocksDB, and perform a system-to-system evaluation. The performance comparison under the YCSB workloads shows that SEMU can efficiently improve RocksDB’s performance while considering data concurrency. In particular, in the multi-thread concurrent environment, SEMU, on average, outperforms LRU, 2Q, FIFO, and FrozenHot by up to 1.9<inline-formula><tex-math>$times$</tex-math></inline-formula>, 1.6<inline-formula><tex-math>$times$</tex-math></inline-formula>, 80%, and 102% under the synthetic workloads, and improves the throughput of RocksDB configured with default settings by up to 59.67% in the system-to-system comparison.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"734-747"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148482341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Latency Implementation of Bitsliced SPN-Cipher on IoT Processors 位片SPN-Cipher在物联网处理器上的低延迟实现

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-12-10 DOI: 10.1109/TC.2025.3642221

Jiahao Xiang;Lang Li

{"title":"Low-Latency Implementation of Bitsliced SPN-Cipher on IoT Processors","authors":"Jiahao Xiang;Lang Li","doi":"10.1109/TC.2025.3642221","DOIUrl":"https://doi.org/10.1109/TC.2025.3642221","url":null,"abstract":"Bitsliced cipher implementations demonstrate enhanced performance and security on high-end processors through specialized instruction utilization. However, IoT processors, particularly 32-bit architectures, present significant implementation challenges due to limited register sizes and instruction sets, hindering efficient parallelism in bitsliced SPN ciphers. This study presents optimization strategies for implementing bitsliced SPN ciphers on 32-bit processors using common instruction sets. The linear layer optimization employs a decomposition algorithm that transforms complex permutation operations into minimal instruction sequences. This approach recursively identifies optimal instruction combinations while maintaining computational efficiency. For the non-linear layer, operations are constrained to basic logic instructions (NOT, AND, OR, XOR). A novel encoding method for the Bit-slice Gate Complexity (BGC) model is proposed to optimize S-box transformations within these constraints using Boolean satisfiability solvers. Additionally, a comprehensive benchmarking framework facilitates standardized performance evaluation across implementations. Experimental evaluation of the optimized implementations on ARM Cortex-M and Xtensa LX processors demonstrates significant performance improvements. The proposed techniques achieve reductions of 9.7% and 67.6% in Cycles Per Byte for AES and QARMAv2 implementations, respectively.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"642-652"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BASE: A Framework for Treating Errors in Stochastic Computing Systems BASE：处理随机计算系统误差的框架

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-10-28 DOI: 10.1109/TC.2025.3626649

Timothy J. Baker;John P. Hayes

引用次数: 0

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-02-01 Epub Date: 2025-10-28 DOI: 10.1109/TC.2025.3626425

Yayong Shi;Rui Wang;Yida Zhang;Handa Chai;Jiahao Wang;Yuan Yao;Haiyan Zhu

{"title":"Similarity-Based Multivariate Data Completion Framework for Emergency Rescue Sensors","authors":"Yayong Shi;Rui Wang;Yida Zhang;Handa Chai;Jiahao Wang;Yuan Yao;Haiyan Zhu","doi":"10.1109/TC.2025.3626425","DOIUrl":"https://doi.org/10.1109/TC.2025.3626425","url":null,"abstract":"This paper focuses on severe variable missingness and variable sparsity in device-edge collaboration. Inference-based methods yield unacceptable reconstruction errors under high missing rates, thus necessitating retransmission. However, this approach can lead to network congestion and even breakdown in emergency response scenarios. To overcome these limitations, we propose a Similarity-based Multivariate Data Completion Framework (SMDCF). Unlike traditional retransmission approaches, SMDCF adopts an innovative similarity-based learning paradigm. For handling variable missingness, the framework retrieves similar samples from offline datasets by analyzing sparse observations and then effectively transfers relevant variables from these reference samples to complement the incomplete data; for handling variable sparsity, SMDCF employs graph neural networks to systematically model three key relationships: inter-sample correlations, inter-variable dependencies, and intra-variable patterns, thereby achieving robust and reliable missing-value inference. Comprehensive experimental results demonstrate that SMDCF consistently delivers superior performance under various data missing scenarios. Notably, even under an extreme 90% missing data rate, our framework reduces the reconstruction error by 8.37%.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"491-502"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0