IEEE Transactions on Computers最新文献

{"title":"eCache: A Sample-Inference-Based Intelligent Cache Scheme for High-Performance SSDs","authors":"Hui Sun;Yinan Fu;Xin Wang;Yi Zhou;Xiao Qin","doi":"10.1109/TC.2025.3628340","DOIUrl":"https://doi.org/10.1109/TC.2025.3628340","url":null,"abstract":"DRAM-based cache is a practical approach to enhancing the performance of large-capacity SSDs. Due to DRAM’s limited capacity, cache sizes are significantly smaller than the data scale of workloads – and cache replacement schemes determine the cache hit ratio and SSD performance when a cache reaches full capacity. Prior work embarked on leveraging machine learning models (ML) to predict future access patterns in workloads, aiding cache replacement decisions for intelligent cache schemes inside SSDs. Unfortunately, existing ML-based cache schemes often overlook the impacts of data granularity – including page, request, and coarse granularities – of training datasets, model inference time overhead, and computational overhead on SSD performance. To address these challenges, we are motivated to propose an sample-inference-based int<bold><i>e</i></b>lligent <bold><i>cache</i></b> scheme – eCache. eCache accurately predicts the future reuse distance of each sampled requested pages, which can enhance the accuracy of decision-making for the cache replacement. In particular, we design a parallel framework to curb the time overhead caused by model inference. We advocate for a random-group sampling inference method that utilizes the most accurate model while reducing computational overhead. Moreover, we implement eCache on the state-of-the-art SSD simulator, MQSim, and compare it against alternative cache schemes (<italic>i.e.,</i> CCache, NCache, LAC, and VS-batch). The experimental results unveil that compared with the other cache schemes, eCache significantly reduces the average response time by up to 79.68% with an average reduction of 44.08%. When compared with the page-granularity-ML-empowered cache schemes, eCache greatly curtails computational overhead by up to 85.23% with an average reduction of 66.00%.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"582-596"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization","authors":"Yuzong Chen;Chi-Chih Chang;Xilai Dai;Ahmed F. AbouElhamayed;Marta Andronic;George A. Constantinides;Mohamed S. Abdelfattah","doi":"10.1109/TC.2025.3628193","DOIUrl":"https://doi.org/10.1109/TC.2025.3628193","url":null,"abstract":"Large language models (LLMs) have achieved significant breakthroughs on machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their wide deployment. In this paper, we propose BitMoD, an algorithm-hardware co-design solution for efficient LLM deployment. On the algorithm side, BitMoD introduces “fine-grained data type adaptation”, which uses a different data type to quantize a group (e.g., 128) of weights and key-value-cache (KV-cache). Through the careful design of these data types, BitMoD is able to quantize LLM weights and KV-cache to sub-4-bit precision while maintaining high accuracy. On the hardware side, BitMoD employs the bit-serial computing to easily support multiple numerical precisions and data types, thus providing a flexible trade-off between model accuracy and hardware efficiency. Furthermore, we design low-cost hardware components to effectively handle online KV-cache quantization and per-group partial sum dequantization. Our evaluation on a diverse set of LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization methods on both discriminative and generative tasks. Combining the superior model performance with an efficient accelerator design, BitMoD surpasses the state-of-the-art LLM accelerator in terms of both hardware performance and energy efficiency.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"567-581"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148478716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Levee: A Blockchain Sharding System Capable of Tolerating Faulty Shards","authors":"Xin Wang;Yanxiu Liu;Linpeng Jia;Yi Sun","doi":"10.1109/TC.2025.3626232","DOIUrl":"https://doi.org/10.1109/TC.2025.3626232","url":null,"abstract":"Sharding is a promising solution to enhance blockchain scalability. While deploying more shards of smaller sizes for a given network scale can significantly boost performance, it also heightens the risk of shard failures. In many existing sharding systems, the failure of a single shard can compromise the entire system. Therefore, to ensure safety, current systems often require each shard to contain hundreds of consensus nodes to prevent crashes, adversely affecting scalability. In this paper, we propose Levee, a blockchain sharding system capable of tolerating shard failures. When a shard malfunctions, Levee can swiftly detect, isolate, and autonomously recover the faulty shard, allowing other shards to operate without interruption. This fault-tolerance feature enables Levee to reduce shard sizes by 73.7% and increase the number of shards by 3.25 times, all without sacrificing security. When tested in a scenario with 7000 nodes, Levee demonstrated a 14.34 times increase in throughput and a 65% decrease in transaction latency compared to traditional non-fault-tolerant sharding systems.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"477-490"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feynman Meets Turing: Computability Aspects of Quantum Compiling Revisited","authors":"Yannik N. Böck;Holger Boche;Zoe Garcia del Toro;Frank H.P. Fitzek","doi":"10.1109/TC.2025.3626469","DOIUrl":"https://doi.org/10.1109/TC.2025.3626469","url":null,"abstract":"We consider a formalism of <italic>quantum compiler functions</i> – functions that map unitary matrices to corresponding gate-circuit approximations – and prove the infeasibility of digitally computing such functions. Since the gate-circuit model of quantum computing emerged, much research has been conducted to find algorithmic solutions to the <italic>quantum compiler problem</i>. The renowned <italic>Solovay-Kitaev theorem</i> proves the existence of quantum compiler functions that provide low-complexity gate-circuit approximations to arbitrary unitary matrices, which is indispensable for the practical feasibility of gate-based quantum computing. However, the mere existence of such functions does not imply their <italic>realizability</i> by means of an <italic>algorithm</i> – a constructive procedure executed by a <italic>Turing machine</i>. In fact, no algorithm for computing any quantum compiler function is known today. The present article demonstrates that no such algorithm can exist. We prove that no quantum compiler function can satisfy <italic>Banach-Mazur computability</i>, which is a formalization of algorithmic feasibility with (mathematically) weak requirements. In consequence, there definitely does not exist a Turing machine that computes any quantum compiler function in the above sense, nor can there exist a <italic>constructive proof</i> of the existence of any such function. Furthermore, we discuss proposed methods of quantum compiling and analyze them in the context of our results.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"516-526"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11219313","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MI-LLM: Multiplier-Free LLM Inference on Commodity Processing-in-Memory Hardware","authors":"Puyun Hu;Minhui Xie;Linjiang Li;Kuiyaohui Zhang;Erge Xiang;Jing Wang;Size Zheng;Xiao Zhang;Yunpeng Chai","doi":"10.1109/TC.2025.3626449","DOIUrl":"https://doi.org/10.1109/TC.2025.3626449","url":null,"abstract":"Large language models (LLMs) are prominent for their superior ability in language understanding and generation. However, a notorious problem for LLM inference is low computational utilization caused by the memory bottleneck, since it typically requires large memory capacity and high bandwidth to process neural weights. By integrating processing cores into memory, Processing-In-Memory (PIM) architecture excels at alleviating memory bottleneck; with the recent release of the first commodity near-bank PIM hardware (NBP), PIM becomes off-the-shelf and shows great potential for accelerating LLM inference practically. However, simply shoehorning LLM inference on NBP can not achieve satisfactory performance due to its inherent limitations: weak compute performance, frequent cache misses caused by the limited working memory capacity, and poor inter-PIM-core communication bandwidth. To address these limitations, we propose <sc>MI-LLM</small>, an efficient system deploying LLM inference on NBP hardware. Its key idea is to build NBP-aware Lookup Tables (LUTs) and completely replace multiplications with lookups on LUTs, thereby mitigating the limitation of weak compute performance. 1) To reduce the model accuracy drop caused by the use of LUT, <sc>MI-LLM</small> tailors a learning-based LUT construction method to maintain the model accuracy. 2) To cope with frequent cache misses caused by LUT sizes far exceeding PIM working memory capacity, <sc>MI-LLM</small> introduces the design of PIM-aware linear kernel, with the optimization of intra-row and inter-row reordering enabled, to enhance LUT lookup locality. 3) <sc>MI-LLM</small> further proposes a model partitioning scheme to minimize inter-PIM-core communication. Kernel-level benchmarks reveal that <sc>MI-LLM</small> achieves a 9% throughput improvement and an 11% increase in energy efficiency over GPU implementations. Compared to FP8 quantization, <sc>MI-LLM</small> incurs only a 0.24 times increase in perplexity, demonstrating minimal accuracy degradation. Moreover, in our end-to-end evaluation, <sc>MI-LLM</small> requires 80% fewer ALU operation ticks per output token than the GPU baseline.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"503-515"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ELS: Efficiency-Aware Dynamic Storage for Scalable Distributed Ledger","authors":"Keke Gai;Chennan Guo;Jing Yu;Qiang Xiao;Weilin Chan;Liehuang Zhu","doi":"10.1109/TC.2025.3626163","DOIUrl":"https://doi.org/10.1109/TC.2025.3626163","url":null,"abstract":"Distributed Ledger Technology (DLT) has emerged as a promising solution for constructing decentralized and trustworthy platforms in recent years. Although blockchain, as a form of distributed ledger technology known for its tamper resistance and trustworthiness, seems to be an ideal solution for addressing trust issues, common blockchain systems face limitations due to the ever-growing volume of data. In this paper, we propose a dynamic storage scheme called <italic><u>E</u>fficiency-aware <u>L</u>ow-storage <u>S</u>calability</i> (ELS), which allocates variable data storage for the distributed ledgers. Our approach is designed to provide load balancing and security, allowing dynamic nodes to join or exit the network seamlessly. We utilize graph theory to group storage nodes in the blockchain by determining their network distances. These groups are then mapped into points in a two-dimensional virtual plane, meaning that block storage depends on the coordinates within the virtual plane. To balance storage performance with the evolving block allocation strategy, we develop a Voronoi diagram-based method to achieve near real-time adoptions that meet dynamic allocation requirements in blockchain systems. Experimental evaluations have demonstrated that our approach can reduce storage requirements by approximately 93% at each node, compared to full replication in 10000 block chains.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"462-476"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerating LLM Inference via Low-Bit Fine-Grained Quantization Algorithm and Bit-Level Accelerator Co-Design","authors":"Xilong Xie;Liang Wang;Limin Xiao;Li Ruan;Tairan Zhang;Jinquan Wang;Yongyue Wang;Xiaojian Liao","doi":"10.1109/TC.2025.3628629","DOIUrl":"https://doi.org/10.1109/TC.2025.3628629","url":null,"abstract":"Large language models (LLMs) have emerged as one of the most impactful and transformative paradigms in natural language processing. Despite their remarkable success, the intensive computational demands and substantial memory footprint impose a significant barrier to efficient LLM inference. In this paper, we present a comprehensive solution to improve LLM inference performance under ultra-low weight precision, meticulously optimized through algorithm and architecture co-design. To achieve this, we first propose a fine-grained intra-cluster bit allocation method that partitions the weights into small clusters and explicitly considers the distribution of outliers and salient points within each cluster. Then, an intra-cluster protection mechanism is proposed to selectively preserve important weights during quantization, where an extended integer format and group-wise scale factor search are further introduced to mitigate accuracy degradation caused by aggressive bit-width reduction. Furthermore, we develop a memory-aligned encoding scheme to facilitate efficient memory access while enabling flexible identification of mixed-precision representations. Finally, we design a lightweight bit-level accelerator for low-bit LLM inference, offering simplified hardware design and enhanced adaptability through parallel bit-level computation. Compared to existing state-of-the-art quantization algorithms, our algorithm achieves higher model accuracy under ultra-low weight precision. Meanwhile, the proposed bit-level accelerator delivers speedups of 1.59<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, 1.38<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, and 1.61<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, along with energy efficiency improvements of 1.52<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, 1.42<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, and 1.22<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> over ANT, OliVe, and FineQ, respectively.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"597-611"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs","authors":"Gabriele Montanaro;Andrea Galimberti;Davide Zoni","doi":"10.1109/TC.2025.3624704","DOIUrl":"https://doi.org/10.1109/TC.2025.3624704","url":null,"abstract":"The design space exploration (DSE) of heterogeneous multi-core systems-on-chip (SoCs) presents a massive challenge due to the vast and complex configuration space, demanding simultaneous optimization of performance, energy efficiency, and resource utilization under diverse constraints. Traditional approaches leveraging analytical models, heuristics, and machine learning (ML) techniques fail to comprehensively cover this space, often yielding suboptimal solutions. The Omega framework, designed for exhaustive DSE of FPGA-based heterogeneous multi-core SoCs, addresses the former limitations by fully exploring the design space and guaranteeing the identification of globally optimal configurations. Omega leverages FPGAs’ dynamic partial reconfiguration to accelerate the DSE drastically and can serve as a golden model for evaluating novel DSE heuristics and ML methods. This manuscript demonstrates the proposed framework’s effectiveness through an extensive experimental campaign on 16-core SoCs with accelerators for up to five different applications, achieving a substantial speedup, of 29 times on average, compared to traditional techniques while ensuring solution optimality. Omega is released as a comprehensive open-source ecosystem, compatible with commercially available FPGA platforms, to facilitate future research and practical adoption, setting a new benchmark for DSE methodologies and providing a robust tool for optimizing next-generation computing platforms.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"435-447"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering","authors":"Lixia Han;Yiyang Chen;Hui Chen;Xueming Fu;Zheng Zhou;Ke Chen;Peng Huang;Yijun Cui;Weiqiang Liu","doi":"10.1109/TC.2025.3642843","DOIUrl":"https://doi.org/10.1109/TC.2025.3642843","url":null,"abstract":"Novel View Synthesis is a foundational technique for creating immersive Augmented and Virtual Reality (AR/VR) experiences, aiming to generate photorealistic images of a scene from arbitrary camera viewpoints using only a limited set of source images, with Neural Radiance Fields (NeRF) emerging as the state-of-the-art solution. However, real-time NeRF rendering on low-power devices remains challenging due to its memory-intensive hash encoding and compute-intensive Multilayer Perception (MLP). In this work, we propose Instant-CIM, the fully on-chip Computing-in-Memory (CIM) architecture for efficient NeRF rendering. At the algorithm level, Instant-CIM proposes a spatially-adaptive framework that dynamically selects the number of active hash encoding levels per spatial region based on a composite importance score derived from density and gradient. The approach replaces uniform level allocation with a threshold-based strategy that activates finer encoding levels only in regions with high representation complexity. At the hardware level, Instant-CIM proposes an in-situ hash engine that implements in-memory hash query and interpolation through 3D scene grid decomposition and Z-order based mapping schemes. Meanwhile, Instant-CIM proposes a sparse MLP engine that leverages differential-based input complemented by a precision-adjustable skipping mechanism to fully exploit spatial similarities. Comprehensive evaluation across synthetic datasets demonstrates that Instant-CIM achieves 3.0<inline-formula><tex-math>$times$</tex-math></inline-formula>∼4.9<inline-formula><tex-math>$times$</tex-math></inline-formula> improvement in rendering speed and 8.6<inline-formula><tex-math>$times$</tex-math></inline-formula>∼33<inline-formula><tex-math>$times$</tex-math></inline-formula> enhancement in energy efficiency compared to state-of-the-art NeRF architecture.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"693-705"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TupleChain: Fast Flow Table Lookup With Efficient On-Line Updates and Scalability","authors":"Yanbiao Li;Neng Ren;Xin Wang;Yuxuan Chen;Xinyi Zhang;Lingbo Guo;Gaogang Xie","doi":"10.1109/TC.2025.3626594","DOIUrl":"https://doi.org/10.1109/TC.2025.3626594","url":null,"abstract":"Packet classification is a fundamental operation in modern network systems, playing a central role in traffic management, security enforcement, and policy execution. While traditional algorithms have achieved low lookup latency in static scenarios, emerging applications impose more demanding requirements—not only fast lookup, but also high-frequency online updates and strong scalability. Existing approaches often struggle to handle large rule sets or support rules with an increasing number of matching fields, making them unsuitable for dynamic and large-scale network environments. In this work, we propose TupleChain for fast on-line update table lookup with multifaceted scalability. We group rules based on their masks, each maintained using a hash table, and explore the connections among rule groups to skip unnecessary hash probes for faster searches. We show via theoretical analysis and extensive experiments that the proposed scheme offers competitive computational complexity, strong scalability, and high performance in both search and update operations. TupleChain can process millions of packets per second, while simultaneously handling millions of on-line updates per second at the same time, and its lookup speed remains stable even when processing large flow table with 10 million rules or entries containing up to 100 match fields.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"527-540"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}