IEEE Transactions on Computers最新文献

A Fast Intermittent Fault Diagnosis Algorithm for a Class of Data Center Networks 一类数据中心网络的快速间歇故障诊断算法

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-14 DOI: 10.1109/TC.2026.3654522

Hui Dong;Huaqun Wang;Mengjie Lv;Weibei Fan

{"title":"A Fast Intermittent Fault Diagnosis Algorithm for a Class of Data Center Networks","authors":"Hui Dong;Huaqun Wang;Mengjie Lv;Weibei Fan","doi":"10.1109/TC.2026.3654522","DOIUrl":"https://doi.org/10.1109/TC.2026.3654522","url":null,"abstract":"As a data center network (DCN) constructed using recursive modules, BCube enables efficient communication for decentralized machine learning systems. Its various variants, such as RCube and RRect, outperform BCube in certain performance metrics. To unify related research, BCube and its variants are integrated into a unified framework known as BCube-based DCNs (BDCN). In practical DCN deployments, efficient fault diagnosis is essential for reliability and stability. However, intermittent faults are more challenging to diagnose than permanent ones due to their randomness and uncertainty. Moreover, existing intermittent fault diagnosis algorithms generally rely on searching for the largest component, which leads to high time complexity. To address this issue, this paper systematically analyzes the intermittent fault diagnosability of BDCN under the PMC model, and proposes a fast intermittent fault diagnosis algorithm (FIFDA). The proposed algorithm significantly improves diagnosis efficiency by avoiding the need to search for the largest component. Extensive experimental results verify the applicability of FIFDA in both BDCN and other high-performance DCNs. Comparative analyses with existing algorithms show that FIFDA achieves higher diagnostic speed. Moreover, under comparable diagnosis times, FIFDA demonstrates superior diagnostic performance. In addition, simulation results demonstrate that FIFDA maintains outstanding performance in large-scale DCNs and under varying noise levels and fault probabilities, fully showcasing its efficiency and scalability in practical DCN environments.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1551-1564"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack 面向可部署的CXL-PNM: CMM-Ax原型和软件堆栈

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-16 DOI: 10.1109/TC.2026.3654850

Kwangsik Shin;Kangkyu Park;Joonseop Sim;Thomas Won ha Choi;Youngpyo Joo;Hoshik Kim

{"title":"Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack","authors":"Kwangsik Shin;Kangkyu Park;Joonseop Sim;Thomas Won ha Choi;Youngpyo Joo;Hoshik Kim","doi":"10.1109/TC.2026.3654850","DOIUrl":"https://doi.org/10.1109/TC.2026.3654850","url":null,"abstract":"Processing-Near-Memory (PNM) over Compute Express Link (CXL) has strong architectural appeal. However, most existing CXL-attached PNM prototypes remain inflexible or simulation-based and lack integration with full software stacks, which limits their practical deployment. This work introduces CMM-Ax, a deployable hybrid CXL-PNM system that combines streaming near-memory pipelines with device-side programmability and integrates tightly with the Heterogeneous Memory Software Development Kit (HMSDK). Through HMSDK, CMM-Ax exposes CXL-attached memory via standard Linux allocation paths (e.g., malloc and mmap). This allows existing vector databases and search engines to adopt heterogeneous memory with minimal application-level changes, such as selecting the CMM-Ax FAISS backend. CMM-Ax further provides a comprehensive software stack—FAISS integration, a domain-specific compiler for user-defined operators, and a Kubernetes device plugin supporting multi-tenant slicing—capabilities not demonstrated in prior CXL-PNM. Using an FPGA-based CXL Type-3 prototype, CMM-Ax achieves 4.54<inline-formula><tex-math>${boldsymboltimes}$</tex-math></inline-formula> higher throughput and 5.56<inline-formula><tex-math>${boldsymboltimes}$</tex-math></inline-formula> lower energy per query than a CXL memory-only baseline on the exact k-nearest neighbor (kNN) search. For approximate nearest neighbor (ANN) inverted-file (IVF) workloads, CMM-Ax sustains bandwidth-proportional efficiency at small batches (batch = 1: 37% vs. 12% CPU, 7% GPU). In Kubernetes deployments, CMM-Ax–equipped servers can replace a significantly larger CPU-only cluster at equivalent memory capacity and throughput, reducing node count and system energy.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1363-1377"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prime Factorization Using Partially Constrained Multiple Quantum Annealing With Analytical and Pattern-Based Variable Reduction 基于解析和模式的变量约简的部分约束多重量子退火的质因数分解

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-15 DOI: 10.1109/TC.2026.3654172

Xinyi Guo;Geguang Miao;Shinichi Nishizawa;Shinji Kimura;Takashi Sato

{"title":"Prime Factorization Using Partially Constrained Multiple Quantum Annealing With Analytical and Pattern-Based Variable Reduction","authors":"Xinyi Guo;Geguang Miao;Shinichi Nishizawa;Shinji Kimura;Takashi Sato","doi":"10.1109/TC.2026.3654172","DOIUrl":"https://doi.org/10.1109/TC.2026.3654172","url":null,"abstract":"Factorization of large semiprimes remains one of the most challenging problems for classical computers. Shor’s algorithm offers a quantum approach that reduces computational complexity, but its practical application is currently limited by hardware constraints. Meanwhile, as a provisional approach, quantum annealing (QA) has been explored through formulations of the quadratic unconstrained binary optimization (QUBO) problem. Among existing methods, the blockwise partial-product approach effectively reduced the QUBO variable count but was limited to semiprimes up to 21 bits. To extend factorization to larger semiprimes, this paper addresses key engineering challenges in constructing efficient QUBO formulations for prime factorization. We propose five techniques to reduce variable counts and improve scalability with current QA hardware: (1) dividing the problem into subproblems with partial constraints; (2) applying analytical reductions near the LSB; (3) applying analytical reductions near the MSB; (4) exploiting special patterns in semiprimes, with odd bit widths and long MSB-side zero sequences; and (5) balancing variable usage across both sides of the subproblem. Integrated into a QUBO converter, these methods enable stable factorization of semiprimes up to 47-bits within 20 seconds and can extend to special 2049-bit instances with 1001 consecutive MSB-side zeros.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1446-1458"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11355721","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

From Good to Great: Parameter Tuning in Memory Tiering Systems 从优秀到卓越：内存分层系统的参数调优

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-21 DOI: 10.1109/TC.2026.3656472

Konstantinos Kanellis;Sujay Yadalam;Hayden Coffey;Shivaram Venkataraman;Michael Swift

{"title":"From Good to Great: Parameter Tuning in Memory Tiering Systems","authors":"Konstantinos Kanellis;Sujay Yadalam;Hayden Coffey;Shivaram Venkataraman;Michael Swift","doi":"10.1109/TC.2026.3656472","DOIUrl":"https://doi.org/10.1109/TC.2026.3656472","url":null,"abstract":"To meet the memory demands of modern data-intensive applications such as graph processing and machine learning, datacenters are adopting tiered memory architectures that include fast tiers such as locally attached DRAM and slower tiers built using CXL-attached memory. While these newer tiers expand capacity, they have higher access latencies and lower bandwidth, which can lead to application performance degradation. To minimize performance loss, frequently accessed (hot) data must be placed close to the CPU in faster tiers and infrequently accessed (cold) data can be placed in farther, slower memory tiers. Existing software-managed tiering solutions employ heuristics and pre-configured thresholds to determine hot and cold data, and make placement and migration decisions. Unfortunately, due to their use of static thresholds, these systems fail to adapt to different workloads and the underlying hardware, and hence perform poorly. In this paper, we study the relationship between thresholds and parameters used by tiering systems and application performance. We leverage Bayesian Optimization to tune the parameters of three tiering systems: HeMem, Memtis, and HMSDK. We find that applications are sensitive to these parameter values, and that best parameter values vary widely across workloads, inputs, thread counts, memory ratios, and hardware characteristics. Our experiments reveal that the Bayesian optimizer can learn workload behaviors and set parameter values that result in best performance. With proper parameter tuning, performance can improve by up to 2x compared to default configurations, highlighting the importance of parameter selection for memory tiering systems.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1378-1390"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems 基于集群的RAG系统的性能分析和CXL内存优化

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2025-12-12 DOI: 10.1109/TC.2025.3643434

Jesin Kim;Hochul Shin;Byeonghun Hwang;Seungpyo Cho;Kyumin Park;Young Geon Yoo;Byungyo Lee;Hojun Shim

{"title":"Performance Analysis and CXL Memory Optimization in Cluster-Based RAG Systems","authors":"Jesin Kim;Hochul Shin;Byeonghun Hwang;Seungpyo Cho;Kyumin Park;Young Geon Yoo;Byungyo Lee;Hojun Shim","doi":"10.1109/TC.2025.3643434","DOIUrl":"https://doi.org/10.1109/TC.2025.3643434","url":null,"abstract":"Retrieval-augmented generation (RAG) systems rely on large-scale embedding search. However, the growth of corpora and the demand for real-time queries expose the memory capacity and bandwidth limitations of DRAM-centric architectures. To address this challenge, we adopt CXL memory in conjunction with cluster-scale RAG deployments and optimize the system in terms of performance, latency and cost efficiency. Our design leverages state-of-the-art CXL memory devices and platforms with memory management policies such as weighted interleaving and tiering between DRAM and CXL memory. In comparison with a DRAM baseline, our system archives 20% higher vector search performance and 43% lower LLM time-to-first token (TTFT), demonstrating clear end-to-end performance benefits. Moreover, in the context of overall system efficiency, we observed up to 20% and 42% improvement in power efficiency (QPS/Watt) and cost efficiency (QPS/$), respectively. These results demonstrate that, despite the relatively high latency of CXL memory, memory management policy-level optimization enable CXL memory to serve as a first-class memory resource in cluster-based RAG systems.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1323-1334"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Highly Cost-Effective and Fault-Tolerant Network Topology for Large-Scale Data Centers 用于大规模数据中心的高成本效益和容错网络拓扑

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-14 DOI: 10.1109/TC.2026.3654209

Weibei Fan;Xiangying Peng;Fu Xiao;Mengjie Lv;Xueli Sun;Wei Duan;Sun-Yuan Hsieh

{"title":"A Highly Cost-Effective and Fault-Tolerant Network Topology for Large-Scale Data Centers","authors":"Weibei Fan;Xiangying Peng;Fu Xiao;Mengjie Lv;Xueli Sun;Wei Duan;Sun-Yuan Hsieh","doi":"10.1109/TC.2026.3654209","DOIUrl":"https://doi.org/10.1109/TC.2026.3654209","url":null,"abstract":"With the rapid advancement of digital technologies such as cloud computing, big data, and artificial intelligence, large-scale data centers have become critical infrastructure supporting these technologies, imposing increasingly high demands on data center networks (DCNs). Traditional server-centric DCNs face challenges in large-scale distributed systems, such as difficulty in balancing bandwidth and latency, high expansion costs, and conflicts between fault tolerance and communication efficiency. To address these issues, this paper proposes ECQDC, a novel server-centric DCN based on exchanged crossed cube. Specifically, we present its logical structure ECD<inline-formula><tex-math>$(s,t)$</tex-math></inline-formula> and study the connectivity and edge connectivity of ECD<inline-formula><tex-math>$(s,t)$</tex-math></inline-formula>. Furthermore, we develop efficient fault-free routing algorithm and fault-tolerant routing algorithm for the ECD<inline-formula><tex-math>$(s,t)$</tex-math></inline-formula>. The experimental results demonstrate that, compared with Dijkstra and BFS, the proposed ECDR and ECDFTR algorithms reduce the average running time by over 50% and cut the average path length by approximately 20% relative to BFS, while keeping path lengths close to Dijkstra’s optimal performance. Moreover, it exhibits excellent performance in scalability, fault tolerance, and communication efficiency, making it an ideal network topology for large-scale data center deployment.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1488-1502"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pangaea v2: CXL-Based Disaggregated Memory System Architecture for Cloud-Native Orchestration Pangaea v2：用于云原生编排的基于cxl的分解内存系统架构

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-20 DOI: 10.1109/TC.2026.3654926

Han Deok Lee;Jehoon Park;Younghyun Lee;Junhyeok Im;Jin Jung;Jinin So;Siamak Tavallaei;Taehoon Lee;Woo Taek Shim;Chin-Hua Chang;Jianping Jiang;Sungwook Ryu;Taeksang Song;Wonhwa Shin;Sangjoon Hwang

{"title":"Pangaea v2: CXL-Based Disaggregated Memory System Architecture for Cloud-Native Orchestration","authors":"Han Deok Lee;Jehoon Park;Younghyun Lee;Junhyeok Im;Jin Jung;Jinin So;Siamak Tavallaei;Taehoon Lee;Woo Taek Shim;Chin-Hua Chang;Jianping Jiang;Sungwook Ryu;Taeksang Song;Wonhwa Shin;Sangjoon Hwang","doi":"10.1109/TC.2026.3654926","DOIUrl":"https://doi.org/10.1109/TC.2026.3654926","url":null,"abstract":"Today’s centers suffer from CPU and memory resource stranding because they often over-provision resources when deploying servers for worst-case scenarios. This problem gives rise to a disaggregated system architecture allowing each type of resource to be allocated, utilized and freed separately as required. In particular, research on disaggregated memory systems over the past few years has focused primarily on achieving low remote memory access latency over Ethernet, which is known as the RDMA optimization approach. In this paper, we introduce a dynamic rack-scale disaggregated memory system architecture, so called <monospace>Pangaea v2</monospace> using ASIC-CXL H/W and memory orchestration S/W designed to increase the memory utilization of worker nodes between containerized applications execution in a Kubernetes, a major process container platform in the data center. In our evaluation with in-memory database application, disaggregated CXL memory system shows significantly better throughput improved by up to 10.2x/6.7x and 99th tail latency reduced to 96%/93% compared to RDMA with RoCEv2/InfiniBand.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1261-1275"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

No Atomics, No Problem. Developing a RAG Pipeline for Shared CXL Memory 没有原子，就没有问题。面向共享CXL内存的RAG管道开发

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-02-24 DOI: 10.1109/TC.2026.3667821

Alfred Bratterud;Gisle Dankel;Amin Farajianzadeh;John Groves;Chengyi Juan;Joshua Suetterlein;Andrés Márquez;Petter Gustad;Arnt Emil Ingulstad

{"title":"No Atomics, No Problem. Developing a RAG Pipeline for Shared CXL Memory","authors":"Alfred Bratterud;Gisle Dankel;Amin Farajianzadeh;John Groves;Chengyi Juan;Joshua Suetterlein;Andrés Márquez;Petter Gustad;Arnt Emil Ingulstad","doi":"10.1109/TC.2026.3667821","DOIUrl":"https://doi.org/10.1109/TC.2026.3667821","url":null,"abstract":"We share early experiments with software development for shared CXL memory on the H3 Falcon C5022 CXL switch. We describe how the different stages in the development of a commercial RAG pipeline were impacted by the presence of CXL memory. All of Wikipedia is split into 46 million text passages which are embedded into a high-dimensional embedding space and subjected to heavy load in single- and multi-host experiments. We observe significant performance advantages available to DuckDB and Faiss without changing the software; we measure up to 12x latency reduction with real workloads and 40x reduction with synthetic workloads on CXL, compared to the same queries run with demand paging on NVMe. We explain the current challenges of working with two disjoint cache coherency domains and explain how the Fabric-Attached Memory File System (famfs) and famfs producer-consumer queues provide synchronization patterns without atomic operations on current x86 CPUs. We then discuss open challenges remaining for high performance atomics and locking mechanisms in shared memory. Lastly we show how famfs page-level interleaving enables near-linear throughput scaling when a second host serves queries from the same Faiss index on shared fabric-attached memory and how shared memory allocations can be orchestrated by Kubernetes in a full vertical RAG deployment.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1291-1308"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Renounce Darkness: Employing Cache Attack for Defending Against Information Leakage in Socket-Based IPC 放弃黑暗：利用缓存攻击防御套接字IPC中的信息泄漏

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-15 DOI: 10.1109/TC.2026.3654263

Tianqi Liu;Yingxu Lai;Xiaoming Liu;Yilin Liu;Haochen Wang

{"title":"Renounce Darkness: Employing Cache Attack for Defending Against Information Leakage in Socket-Based IPC","authors":"Tianqi Liu;Yingxu Lai;Xiaoming Liu;Yilin Liu;Haochen Wang","doi":"10.1109/TC.2026.3654263","DOIUrl":"https://doi.org/10.1109/TC.2026.3654263","url":null,"abstract":"Socket-based IPC is widely adopted by local applications, yet it remains vulnerable to Man-in-the-Machine (MitMa) attacks, in which local unprivileged users can intercept or tamper with sensitive information. To reduce the attack surface of MitMa, we present <sc>Cache Cable, which transmits sensitive information covertly to defend against leakage. <sc>Cache Cable is the first defense-oriented use of cache covert channels, repurposed as secure endpoints for transmitting sensitive information. It integrates with socket-based IPC and dynamically activates a covert cache channel, referred to as a <italic>cable, only when sensitive information needs to be sent. We design a secure and noise-resilient communication protocol, along with an application-layer protocol that ensures the reliable establishment of <italic>cables. Our implementation demonstrates that <sc>Cache Cable achieves reliable, error-free transmission rates of up to 497 KB/s with minimal overhead. It effectively resists impersonation, wiretapping, tampering, and jamming attacks under the strong MitMa threat model. Evaluations show that <sc>Cache Cable enhances data confidentiality without sacrificing compatibility or introducing significant overhead, making it suitable for protecting sensitive interactions in widely used local applications.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1503-1517"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tackling Heterogeneity in Quantum Federated Learning: An Integrated Sporadic-Personalized Approach 解决量子联邦学习中的异质性：一种集成的零星-个性化方法

IF 4.9 2区计算机科学

IEEE Transactions on Computers Pub Date : 2026-04-01 Epub Date: 2026-01-14 DOI: 10.1109/TC.2026.3654037

Ratun Rahman;Shaba Shaon;Dinh C. Nguyen

{"title":"Tackling Heterogeneity in Quantum Federated Learning: An Integrated Sporadic-Personalized Approach","authors":"Ratun Rahman;Shaba Shaon;Dinh C. Nguyen","doi":"10.1109/TC.2026.3654037","DOIUrl":"https://doi.org/10.1109/TC.2026.3654037","url":null,"abstract":"Quantum federated learning (QFL) emerges as a powerful technique that combines quantum computing with federated learning to efficiently process complex data across distributed quantum devices while ensuring data privacy in quantum networks. Despite recent research efforts, existing QFL frameworks struggle to achieve optimal model training performance primarily due to inherent heterogeneity in terms of (i) quantum noise where current quantum devices are subject to varying levels of noise due to varying device quality and susceptibility to quantum decoherence, and (ii) heterogeneous data distributions where data across participating quantum devices are naturally non-independent and identically distributed (non-IID). To address these challenges, we propose a novel integrated sporadic-personalized approach called SPQFL that simultaneously handles quantum noise and data heterogeneity in a single QFL framework. It is featured in two key aspects: (i) for quantum noise heterogeneity, we introduce a notion of sporadic learning to tackle quantum noise heterogeneity across quantum devices, and (ii) for quantum data heterogeneity, we implement personalized learning through model regularization to mitigate overfitting during local training on non-IID quantum data distributions, thereby enhancing the convergence of the global model. Moreover, we conduct a rigorous convergence analysis for the proposed SPQFL framework, with both sporadic and personalized learning considerations. Theoretical findings reveal that the upper bound of the SPQFL algorithm is strongly influenced by both the number of quantum devices and the number of quantum noise measurements. Extensive simulation results in real-world datasets also illustrate that the proposed SPQFL approach yields significant improvements in terms of training performance and convergence stability compared to the state-of-the-art methods.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1418-1432"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0