IEEE Transactions on Computers最新文献

{"title":"A Flash-Based Reconfigurable QCNN Inference Accelerator for Edge Applications","authors":"Kyler R. Scott;Sunil P. Khatri","doi":"10.1109/TC.2026.3654441","DOIUrl":"https://doi.org/10.1109/TC.2026.3654441","url":null,"abstract":"This paper presents a novel in-memory flash-based Quantized Convolutional Neural Network (QCNN) inference accelerator Integrated Circuit (IC), which achieves extremely high throughput and extremely low power, energy, and memory requirements. In this manner, our design significantly improves upon state-of-the-art inference accelerators operating at the edge. Our accelerator IC is designed as a field-programmable, reconfigurable dataflow architecture, which allows a wide variety of trained QCNN models to be programmed to our IC. Once programmed with a model, our IC performs inference with <i>zero</i> access to off-chip memory. In our accelerator, the core computing structures are arrays of flash Field Effect Transistors (FETs) integrated in three dimensions (3D). We use 3D NOR flash stacks, thus achieving an area efficient design with the promise of further improvements as the depth of 3D NOR flash process technology advances. Our flash arrays perform dot product operations in the analog voltage domain, using an extremely low supply voltage (<inline-formula><tex-math>$VDD_{lo}$</tex-math></inline-formula>, which is 100 mV in our design), resulting in a very high energy efficiency. The digital I/Os of our arrays are in the nominal supply voltage domain for our process (<inline-formula><tex-math>$VDD_{hi}$</tex-math></inline-formula>, which is 0.8 V in our design), which allows them to be easily stored in registers without the need for level shifters. Neuron weights in our QCNN accelerator are stored in-memory in our flash arrays. These arrays perform dot product operations between a vector of all neuron inputs (in the <inline-formula><tex-math>$VDD_{hi}$</tex-math></inline-formula> domain) and a vector of corresponding weights (stored in the flash devices as programmed <inline-formula><tex-math>$V_{TH}$</tex-math></inline-formula> values), resulting in an output in the <inline-formula><tex-math>$VDD_{lo}$</tex-math></inline-formula> domain. We show that for inference on ImageNet with a quantized AlexNet model, our IC achieves extremely low inference latency (28.7 ms at most), power consumption (5.82 mW at most), and energy consumption (4.35 <inline-formula><tex-math>$mu$</tex-math></inline-formula>J at most), making it especially suited for use in resource-constrained edge devices, such as portable medical devices used for disease diagnosis and ECG signal classification. We prove that our design is robust to Process, Voltage, and Temperature (PVT) variations, and report a drop in Top-1 (Top-5) ImageNet validation accuracy of at most 0.90% (1.07%) across PVT variations. We compare our QCNN accelerator against recent state-of-the-art in-memory neural network accelerators and report an energy efficiency that is at least 15.2<inline-formula><tex-math>$times$</tex-math></inline-formula> higher and a parameter density that is at least 3.32<inline-formula><tex-math>$times$</tex-math></inline-formula> higher than the best existing design.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1533-1550"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FBRE: Fuzzing Based Bit-Level Reverse Engineering of Vehicular CAN Bus","authors":"Hanxue Shi;Yunlang Cai;Xiaohang Wang;Haoting Shen;Li Lu;Kui Ren;Kaiwei Wu;Yinhe Shen","doi":"10.1109/TC.2025.3647888","DOIUrl":"https://doi.org/10.1109/TC.2025.3647888","url":null,"abstract":"The Controller Area Network (CAN) bus serves as a foundational communication architecture in modern vehicles, supporting a wide range of functions, from engine control to auxiliary systems. However, lacking built-in security mechanisms makes CAN vulnerable to cyberattacks. Accurately mapping CAN signals to specific car-control actions becomes critical as it allows the detection of security breaches by pinpointing potential vulnerabilities exploited to compromise vehicular functions. Existing mapping techniques rely on CAN reverse engineering, which struggle to achieve bit-level resolution due to the huge search space of IDs and payload combinations. To address this challenge, we propose a systematic framework that includes signal boundary identification, targeted fuzz testing, and control bit analysis. Our method achieves high efficiency and precision in mapping control bits in CAN frames to car-control actions. Additionally, we developed a compact and user-friendly reverse engineering toolkit, incorporating a graphical interface to facilitate practical vehicle function testing and CAN message monitoring. Experiments on Tesla Model 3 and Leapmotor C11/C10 demonstrate that our framework is validated across different vehicle models and capable of identifying a wide range of car-control actions. Compared with previous works, our method significantly improves the resolution and automation of CAN reverse engineering.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1403-1417"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editors’ Introduction: Special Issue on CXL(®)","authors":"Debendra Das Sharma;Gustavo Alonso;Guangyu Sun","doi":"10.1109/TC.2026.3666079","DOIUrl":"https://doi.org/10.1109/TC.2026.3666079","url":null,"abstract":"","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1232-1233"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11435996","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"S-Tiering: A Unified HW/SW Solution for Memory Tiering Based on the Standard CXL Hotness Monitoring Unit","authors":"Seunghak Lee;Wonjae Lee;Hojin Nam;Jehoon Park;Youngshin Park;Heesoo Kim;Junhyeok Im;Jinin So;Raghu Vamsi Krishna Talanki;Praful Ramesh O;Rajeev Verma;Taeksang Song;Wonhwa Shin;Sangjoon Hwang","doi":"10.1109/TC.2026.3655315","DOIUrl":"https://doi.org/10.1109/TC.2026.3655315","url":null,"abstract":"In this paper, we propose <monospace>S-Tiering</monospace>, a unified hardware and software solution for memory tiering based on the standard CXL Hotness Monitoring Unit (CHMU). <monospace>S-Tiering</monospace> consists of hardware components that comply with CHMU hardware specification defined in the CXL 3.2 Specification, and software components that control hardware components. Based on these components, <monospace>S-Tiering</monospace> minimizes the access to CXL memory by properly steering page migration. We evaluate various probabilistic data structure algorithms and adopt a Count-Min Sketch-based Hot Page Tracker that achieves 99% accuracy with only 0.3% tracking buffer overhead compared to assigning a dedicated counter for every 4 KB page. We implement hardware components of <monospace>S-Tiering</monospace> on an Field-Programmable Gate Array board and software components of <monospace>S-Tiering</monospace> on Ubuntu 22.04 with Linux-v6.8 kernel. We evaluate the performance impact of <monospace>S-Tiering</monospace> on benchmarks representative of real applications (e.g., High Performance Computing, Graph-processing, In-Memory Database). <monospace>S-Tiering</monospace> achieves a performance improvement of up to 193% compared to first-touch allocation and outperforms AutoNUMA memory tiering by 184%p. <monospace>S-Tiering</monospace> minimizes the memory access to CXL memory and increases the bandwidth utilization of DDR memory up to <inline-formula><tex-math>$11times$</tex-math></inline-formula>.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1247-1260"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scaling","authors":"Rui Xie;Asad Ul Haq;Yunhua Fang;Linsen Ma;Zirak Burzin Engineer;Liu Liu;Tong Zhang","doi":"10.1109/TC.2026.3666458","DOIUrl":"https://doi.org/10.1109/TC.2026.3666458","url":null,"abstract":"LLM inference is increasingly limited by memory bandwidth, and the bottleneck worsens at long context as the KV cache grows. CXL memory adds capacity to offload weights and KV, but its link and device-side DDR bandwidth are far below HBM, so decoding stalls once traffic shifts to the CXL tier. Many CXL controllers are starting to add generic <i>lossless</i> compression, yet applying commodity codecs directly to standard word-major LLM tensors is largely ineffective, especially for token-major KV streams. We propose TRACE (<b>T</b>raffic-<b>R</b>educed <b>A</b>rchitecture for <b>C</b>ompression and <b>E</b>lasticity), which preserves the unmodified CXL.mem interface but changes the device-internal representation. It stores tensors in a channel-major, disaggregated bit-plane layout, and applies a KV-specific transform before compression, converting mixed-field words into low-entropy plane streams that commodity codecs can compress. The same substrate enables precision-proportional fetch by reading only the required bit-planes. Across public LLMs, TRACE reduces BF16 weight footprint by 25.2% and BF16 KV footprint by 46.9% losslessly, with per-layer KV ratios peaking at 2.69<inline-formula><tex-math>$times$</tex-math></inline-formula>. In trace-driven system modeling, once KV spills to CXL, GPT-OSS-120B-MXFP4 improves throughput at 128k tokens from 16.28 to 68.99 tok/s (4.24<inline-formula><tex-math>$times$</tex-math></inline-formula>). DRAMSim3 shows up to 40.3% lower DRAM access energy under plane-aligned fetch. A 7 nm SystemVerilog implementation sustains 256 GB/s device bandwidth. Relative to a CXL controller with generic inline lossless compression, TRACE only adds 7.2% area, 4.7% power, and 6.0% load-to-use latency at 2 GHz and 0.7 V.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1349-1362"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Tensor Offloading Based on CXL Memory Pool for Extreme Scale Deep Learning","authors":"Yue Ma;Dongwei Xu;Peng He;Hao Fu;Ying Jing;Sheng Zhang;Fangming Liu;Bowen Wang;Haiyuan Wan;Zhirun Yue","doi":"10.1109/TC.2026.3657493","DOIUrl":"https://doi.org/10.1109/TC.2026.3657493","url":null,"abstract":"The exponential growth of deep learning models imposes severe memory constraints on GPUs, significantly increasing training costs. The prevailing solution for addressing memory constraints is tensor offloading, exemplified by ZeRO-Infinity, which leverages GPUs, CPUs, and NVMe SSDs to enable large-scale model training. However, ZeRO-Infinity faces significant performance bottlenecks due to memory access imbalance, coarse-grained tensor transfers, NVMe bandwidth and latency limits, and software complexity. Compute Express Link (CXL) emerges as a promising technology for building disaggregated memory pools, yet its integration into large-scale training remains underexplored. This paper introduces an efficient CXL memory pool into the system for tensor offloading and leveraging CXL protocol features for hardware acceleration. The proposed design incorporates NUMA-aware memory allocation and a Dynamic Adaptive Pipelining (DAP) strategy to enhance communication–computation overlap, along with a hybrid object-based memory management scheme to mitigate fragmentation and improve allocation efficiency. Experimental evaluation on an 8-GPU system with CXL Type-3 expansion cards demonstrates up to 72.7% throughput improvement, 62.9% latency reduction, and support for training 1.14<inline-formula><tex-math>$times$</tex-math></inline-formula> larger models compared with SSD-based ZeRO-Infinity. This is the first work to integrate CXL with ZeRO-Infinity for large-scale training, offering practical insights for future CXL-based heterogeneous systems.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1335-1348"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CXLock: Efficient and Scalable Lock Management for CXL-Enabled Distributed Systems","authors":"Tao Huang;Yudi Qiu;Yuxin Tang;Qixiao Liu;Wenpu Hu;Xinjun Yang;Yingqiang Zhang;Hao Chen;Guoqiang Xu;Zipeng Ouyang;Yuemin Wu;Jian Chen;Wei Wang;Yang Kong","doi":"10.1109/TC.2026.3658040","DOIUrl":"https://doi.org/10.1109/TC.2026.3658040","url":null,"abstract":"Efficient lock management is critical in distributed systems with shared resources, especially in the context of enhanced computational power and reduced processing time. While numerous studies have leveraged Remote Direct Memory Access (RDMA) for distributed locking, these network-based approaches suffer from high network latency and jitter. The emergence of the Compute Express Link (CXL) protocol provides high-speed, low-latency connections between host processors and memory devices, presenting a compelling alternative for the lock system design. This paper introduces CXLock, the industry’s first distributed lock management system based on CXL 2.0 switches. CXLock decouples lock management into client-side queuing and manager-side arbitration, resolving race conditions of multiple clients without using remote atomics. To handle the lack of hardware-enforced coherence in CXL 2.0, CXLock employs a software-based coherence model that enables memory sharing across multiple hosts with cacheable and write-back attributes. CXLock is implemented and evaluated on a real rack-scale hardware platform containing a CXL switch and multiple host nodes. The results show that CXLock delivers an average throughput improvement of 3.7<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> over the RDMA-based solutions. Moreover, CXLock reduces the lock grant latency by up to 76% in both contention-free and contended scenarios.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1391-1402"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mitigating Priority Inversion in Non-Preemptive Rigid Gang Scheduling Beyond Work-Conserving","authors":"Yonghui Liang;Hui Li;Qimin Xu;Fei Shen;Shanying Zhu;Xinping Guan","doi":"10.1109/TC.2026.3654205","DOIUrl":"https://doi.org/10.1109/TC.2026.3654205","url":null,"abstract":"Rigid gang scheduling, which enables multiple threads of real-time tasks to execute concurrently on a fixed number of different processors, has recently gained attention. Compared to preemptive rigid gang scheduling, non-preemptive rigid gang (NPRG) scheduling improves predictability by requiring fewer context switches. However, NPRG scheduling is vulnerable to 2D-blocking, where lower-priority tasks can block a higher-priority task multiple times, leading to severe priority inversion at runtime and pessimism in schedulability analysis. The root cause is the work-conserving execution behavior, in which tasks are immediately executed whenever the required processors are idle, regardless of priority and the potential blocking of subsequent tasks. This paper focuses on the global fixed-priority NPRG scheduling and introduces the NPRG-SS scheduler. NPRG-SS leverages a selective stalling (SS) mechanism that selectively stalls lower-priority jobs whenever their execution could delay the start time of a higher-priority job in the ready queue. This non-work-conserving approach inherently mitigates multiple blocking. Additionally, we present the first schedulability analysis for NPRG scheduling with SS and propose a novel heuristic priority assignment technique, Iterative Priority Refinement (IPR). Experimental results show that NPRG-SS with IPR effectively mitigates priority inversion, accepts up to 42% more task sets than the baselines at runtime, while our proposed schedulability test accepts up to 80% more task sets than the baselines in worst-case scenarios.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1459-1472"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal Fault-Tolerant Path and Cycle Embedding of Hypercube Networks Under the PEF Model","authors":"Hongbin Zhuang;Wanling Lin;Jou-Ming Chang;Xiao-Yan Li;Xiaohua Jia","doi":"10.1109/TC.2026.3654555","DOIUrl":"https://doi.org/10.1109/TC.2026.3654555","url":null,"abstract":"The hypercube serves as a high-performance interconnection network employed in various fields, including data center networks, network-on-chips, and wireless sensor networks. As the number of processing elements rapidly increases, these application fields are facing significant challenges in preserving communication efficiency with robust fault-tolerant mechanisms. Paths and cycles are two effective and popular tools for improving the communication efficiency of large-scale networks. Fault-tolerant path/cycle embedding is recognized as a solution to maintain communication efficiency and fault tolerance simultaneously. In this paper, we aim to enhance the fault-tolerant path/cycle embedding capability of hypercube networks by an emerging fault model, namely the <underline>P</u>artitioned <underline>E</u>dge <underline>F</u>ault (PEF) model. Under this model, we put forward four distinct fault-tolerant path/cycle embedding algorithms that can handle large-scale faulty edges. Moreover, by proving the upper bound of these algorithms’ fault tolerance, we derive the optimal fault-tolerant Hamiltonian laceability and bipancyclicity of hypercubes under the PEF model. Furthermore, we conduct both theoretical and experimental analyses to show our algorithms’ outstanding fault-tolerant capability compared to the state-of-the-art. To validate the practical applicability of our theoretical results, we also develop a deadlock-free routing strategy leveraging the proposed embedding algorithm and compare its performance with benchmark routing algorithms.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1565-1578"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Communication-Efficient Federated Learning by Exploiting Spatio-Temporal Correlations of Gradients","authors":"Shenlong Zheng;Zhen Zhang;Yuhui Deng;Geyong Min;Lin Cui","doi":"10.1109/TC.2026.3654074","DOIUrl":"https://doi.org/10.1109/TC.2026.3654074","url":null,"abstract":"Communication overhead is a critical challenge in federated learning, particularly in bandwidth-constrained networks. Although many methods have been proposed to reduce communication overhead, most focus solely on compressing individual gradients, overlooking the temporal correlations among them. Prior studies have shown that gradients exhibit spatial correlations, typically reflected in low-rank structures. Through empirical analysis, we further observe a strong temporal correlation between client gradients across adjacent rounds. Based on these observations, we propose GradESTC, a compression technique that exploits both spatial and temporal gradient correlations. GradESTC exploits spatial correlations to decompose each full gradient into a compact set of basis vectors and corresponding combination coefficients. By exploiting temporal correlations, only a small portion of the basis vectors need to be dynamically updated in each round. GradESTC significantly reduces communication overhead by transmitting lightweight combination coefficients and a limited number of updated basis vectors instead of the full gradients. Extensive experiments show that, upon reaching a target accuracy level near convergence, GradESTC reduces uplink communication by an average of 39.79% compared to the strongest baseline, while maintaining comparable convergence speed and final accuracy to uncompressed FedAvg. By effectively leveraging spatio-temporal gradient structures, GradESTC offers a practical and scalable solution for communication-efficient federated learning.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 4","pages":"1433-1445"},"PeriodicalIF":4.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}