IEEE Transactions on Computers最新文献

{"title":"FeFET-Based Analog In-Memory Computing With Inherent Shift-and-Add Capability","authors":"Zeyu Yang;Qingrong Huang;Yu Qian;Jiahao Cai;Min Zhou;Kai Ni;Thomas Kämpfe;Zheyu Yan;Xunzhao Yin;Cheng Zhuo","doi":"10.1109/TC.2026.3662915","DOIUrl":"https://doi.org/10.1109/TC.2026.3662915","url":null,"abstract":"In-memory computing (IMC) architecture has emerged as a highly promising approach, enhancing the energy efficiency of multiply-and-accumulate (MAC) operations in deep neural networks (DNNs) by embedding parallel computations directly into memory arrays. However, existing ferroelectric FET (FeFET)-based analog IMC designs are often constrained to cell-level optimizations and struggle to achieve high-precision MAC operations. In contrast, high-precision analog IMC architectures typically perform MAC operations for partial inputs and weights within the array in a single cycle and then accumulate partial results over multiple cycles. During this procedure, circuits that handle weight shift-and-add process, whether in digital or analog form, incur significant overhead. This paper presents energy-efficient high-precision analog IMC designs leveraging FeFET technology, which inherently support a shift-and-add mechanism for weights. Initially, we introduce an IMC array paradigm that performs partial MAC operations within each column, and seamlessly incorporates the shift-and-add process for weights by utilizing the analog storage properties of FeFET-based cells. Building upon this paradigm, we propose single-level cell (SLC) FeFET-based designs, namely CurFe and ChgFe, operating in the current and charge modes, respectively. Additionally, to leverage FeFET’s multi-level cell (MLC) properties, we propose a novel hybrid SLC-MLC FeFET-based design, MulFe, which offers higher storage density and energy efficiency. Comprehensive evaluations are conducted at both the circuit and system levels, and the results indicate that the average energy efficiency of the proposed FeFET-based analog IMC designs is 1.32<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> to 2.71<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> higher compared to state-of-the-art (SOTA) IMC designs.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 5","pages":"1863-1877"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detecting Faulty Substructures in Networks","authors":"Chen Guo;Guoxuan Zhong;Zhifang Xiao;Dajin Wang","doi":"10.1109/TC.2026.3661204","DOIUrl":"https://doi.org/10.1109/TC.2026.3661204","url":null,"abstract":"The traditional, well-known system-level fault diagnosis is to precisely identify faulty nodes in a network via mutual testing between the nodes, and the <i>diagnosability</i> is the maximum allowed number of faulty nodes for correct diagnosis. This paper proposes a new scheme that focuses on detecting whether a given critical substructure (e.g., a specific cycle or path) contains any faulty node. If the detecting outcome is “Yes”, the entire substructure is deemed as faulty, regardless of how many faulty nodes, and where they are in the substructure. This approach is often more cost-effective and technically feasible than pinpointing every faulty node. We name the maximum allowed number of faulty nodes for this strategy to work as the <b><i>Detectability</i></b> of the network, as opposed to the diagnosability. We study the detectability for the hypercube <inline-formula><tex-math>$Q_{n}$</tex-math></inline-formula>, under the PMC model. We will show that in <inline-formula><tex-math>$Q_{n}$</tex-math></inline-formula> (<inline-formula><tex-math>$ngeq 7$</tex-math></inline-formula>), the detectability is <inline-formula><tex-math>$2n-1$</tex-math></inline-formula> for the minimal bipartite subgraph <inline-formula><tex-math>$K_{1,1}$</tex-math></inline-formula>, and <inline-formula><tex-math>$4n-5$</tex-math></inline-formula> for the 4-node cycle <inline-formula><tex-math>$C_{4}$</tex-math></inline-formula>. Notably, detectability consistently exceeds traditional diagnosability, tolerating more faulty nodes. We have also designed, validated, and implemented detection algorithms of <inline-formula><tex-math>$O(ncdot 2^{n-1})$</tex-math></inline-formula> complexity to detect faulty <inline-formula><tex-math>$K_{1,1}$</tex-math></inline-formula> and <inline-formula><tex-math>$C_{4}$</tex-math></inline-formula> in <inline-formula><tex-math>$Q_{n}$</tex-math></inline-formula>. Simulations show a 100% detection rate, with effectiveness maintained even in lower-dimensional <inline-formula><tex-math>$Q_{n}$</tex-math></inline-formula> where theoretical assumptions do not fully hold.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 5","pages":"1937-1948"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Evaluation of Advanced YOLOv10 and YOLOv11 Architectures for Object Detection in Autonomous Driving Scenarios","authors":"Safa Teboulbi;Seifeddine Messaoud;Mohamed Ali Hajjaji;Mohamed Atri;Abdellatif Mtibaa","doi":"10.1109/TC.2026.3666452","DOIUrl":"https://doi.org/10.1109/TC.2026.3666452","url":null,"abstract":"Autonomous driving technologies are rapidly advancing, driven by the need for safer, more efficient, and intelligent transportation systems. A fundamental component of these systems is the perception module, which enables vehicles to understand and react to their surrounding environment. Object detection, in particular, is essential for identifying dynamic and static elements on the road, such as pedestrians, vehicles, traffic signs, and obstacles. In this work, we explore and enhance the capabilities of state-of-the-art deep learning-based object detectors within the YOLO (You Only Look Once) family, focusing on the latest versions: YOLOv10 and YOLOv11. We fine-tuned and optimized multiple variants of each model—namely, nano (n), small (s), medium (m), and large (l)—to improve detection accuracy and computational efficiency for real-time autonomous driving applications. The models were trained and evaluated on a diverse road object, and performance was measured using key metrics including precision, mean Average Precision (mAP), and Precision-Recall curves. Experimental results reveal that the fine-tuned YOLOv10n achieved a peak class-level precision of 1.00 at a specific confidence threshold (0.997), indicating that perfect precision was observed for certain classes under high-confidence conditions, while the overall mean precision and mAP metrics reflect more balanced model performance, while YOLOv11s attained the best result within its group with a precision of 0.91 at a threshold of 0.972. These findings demonstrate the potential of tailored YOLO architectures to meet the demanding requirements of real-world autonomous navigation systems.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 5","pages":"1949-1965"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EBM: Traffic-Based Differentiated Enhanced Buffer Management in Data Center Networks","authors":"Fu Xiao;Huipeng Huang;Weibei Fan;Mengjie Lv;Xueli Sun;Yiping Zuo;Sun-Yuan Hsieh","doi":"10.1109/TC.2026.3671681","DOIUrl":"https://doi.org/10.1109/TC.2026.3671681","url":null,"abstract":"With the rapid advancement of big data processing and artificial intelligence (AI), data center networks (DCNs) must deliver more efficient resource management and data transmission mechanisms. Unfortunately, due to the significant differences in bandwidth requirements, transmission patterns, and temporal characteristics across various traffic types in DCNs (such as short flows, long flows, and bursty flows), traditional buffer allocation strategies fail to adapt flexibly to these disparities. In this paper, we propose Enhanced Buffer Management (EBM), a novel buffer-sharing scheme designed for scenarios that require higher performance from DCNs. Unlike prior approaches, EBM employs a multi-level flow identification and adaptive threshold adjustment mechanism to enhance the flexibility and efficiency of buffer management under varying traffic conditions. Specifically, EBM first performs coarse-grained and fine-grained classification of traffic based on packet size, inter-arrival interval, and other flow characteristics. It then applies an improved threshold computation function to allocate buffer space differentially across traffic classes while maintaining allocation smoothness. Our evaluation results demonstrate that EBM significantly improves performance under realistic workloads. For instance, it reduces the 99th percentile Flow Completion Time (FCT) slowdown by 32.7% for short flows in the web-search workload and by 45.1% for incast flows in the hadoop workload, all without sacrificing overall throughput.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 5","pages":"1737-1751"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering","authors":"Seongjoon Cho;Junyoung Park;Donghyun Kang;Moohyeon Nam;Hongchan Roh;Moo-Kyoung Chung;Se-Hyun Yang;Seungkyu Choi","doi":"10.1109/TC.2025.3644935","DOIUrl":"https://doi.org/10.1109/TC.2025.3644935","url":null,"abstract":"Similarity search has drawn significant attention due to the growing demand for AI prompt engineering, which leverages retrieval-augmented generation (RAG) systems to maximize the efficiency of large language models (LLMs). Improving the performance of memory-intensive data retrieval processes using approximate nearest neighbor search (ANNS) algorithms has become increasingly crucial for delivering high-quality generative AI services. In this work, we propose Q-VESA, a software-hardware collaborative solution designed to accelerate low-precision graph-based vector search while preserving recall rates comparable to high-precision. We perform a comprehensive analysis of hierarchical navigable small-world (HNSW), one of the most promising graph-based ANNS methods, using recent datasets tailored for RAG systems. Unlike standard vector database datasets, vector data used in LLMs present unique challenges for low-precision search. To address these, we introduce software-oriented precision partitioning techniques that enable mixed-precision computations during graph traversal without compromising hardware performance. The Q-VESA architecture is developed with two key innovations: a database restructuring scheme with vector data segments, and a dedicated accelerator design to maximize throughput in distance computations. Experimental results demonstrate that Q-VESA on a CPU system achieves query-per-second (QPS) speedups of up to 1.81<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> in the SIMD execution mode. Furthermore, leveraging minimal area overhead, the ASIC implementation delivers an additional speedup of up to 58.3<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>, 16.5<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> and 1.5<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> compared to the CPU, GPU and the state-of-the-art ASIC-based accelerator, respectively.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 3","pages":"1028-1042"},"PeriodicalIF":4.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2025 Reviewers List","authors":"","doi":"10.1109/TC.2026.3652671","DOIUrl":"https://doi.org/10.1109/TC.2026.3652671","url":null,"abstract":"","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 3","pages":"1224-1231"},"PeriodicalIF":3.8,"publicationDate":"2026-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11393623","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146154400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient and Secure Information Management Approach for Remote PPG Biometric Authentication Systems","authors":"Liping Zhang;Wenjie Deng;Hewen Pan;Bohao Li;Kim-Kwang Raymond Choo;Jing Chen","doi":"10.1109/TC.2025.3642581","DOIUrl":"https://doi.org/10.1109/TC.2025.3642581","url":null,"abstract":"Despite the fact that biometric systems won many desirable advantages such as high security and convenience, biometric data are vulnerable to various attacks. Once the biometric data are compromised during any point of the authentication process, they are lost forever. In this paper, we propose a security information management approach to address privacy concerns emerging from the management of biometric data in remote Photoplethysmogram (rPPG) biometric authentication systems. In our design, Fully Homomorphic Encryption (FHE) is introduced to protect PPG signals in the transmission and storage phases. We further design an efficient FHE-based Convolutional Neural Network (CNN) model and encrypt the key model parameters of the CNN to realize secure inference. In addition, Principal Component Analysis, Max-Relevance and Min-Redundancy, and Relative Mutual Information methods are employed in the feature extraction stage to screen out the most representative PPG features, thus improving the accuracy of PPG authentication. In the experiments, we adopt eight publicly PPG/rPPG databases and our own rPPG dataset collected via a remote camera to evaluate our proposed biometric authentication system. The experimental results show that our proposed remote PPG biometric authentication system outperforms the state-of-the-art related work in terms of balancing authentication accuracy and biometric privacy protection.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"680-692"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A High-Performance Sketch With Dynamic Memory Allocation for Priority-Oriented Data Stream Processing","authors":"Jinbin Hu;Houqiang Shen;Jiawei Huang;R. Simon Sherratt;Jin Wang","doi":"10.1109/TC.2025.3643356","DOIUrl":"https://doi.org/10.1109/TC.2025.3643356","url":null,"abstract":"Sketch is widely used in many traffic estimation tasks due to its good balance among accuracy, speed, and memory usage. In scenarios with priority flows, priority-aware sketch, as an emerging method, provides differentiated detection accuracy for flows of different priorities, optimizing resource allocation and improving the detection accuracy of high-priority flows. However, existing priority-aware sketches methods struggle to effectively handle the dynamic changes in flow priority distribution in real-world detection environments, leading to wasted or insufficient storage space. To address this issue, this paper proposes a new priority-aware sketch with Dynamic Memory Allocation called DMA-Sketch. It dynamically adjusts the detection framework based on flow priority distribution information and adaptively allocates appropriate memory space to each storage region. The experimental results show that DMA-Sketch improves the overall priority accuracy, high-priority accuracy and throughput by up to 1.33<inline-formula><tex-math>$times$</tex-math></inline-formula>, 16.39<inline-formula><tex-math>$times$</tex-math></inline-formula> and 1.88<inline-formula><tex-math>$times$</tex-math></inline-formula>, respectively, under the scenarios with changing flow priority distribution over the state-of-the-art schemes.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"720-733"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148479073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Object as a Service: Simplifying Cloud-Native Development Through Serverless Object Abstraction","authors":"Pawissanutt Lertpongrujikorn;Mohsen Amini Salehi","doi":"10.1109/TC.2025.3623602","DOIUrl":"https://doi.org/10.1109/TC.2025.3623602","url":null,"abstract":"The function-as-a-service (FaaS) paradigm is envisioned as the next generation of cloud computing systems that mitigate the burden for cloud-native application developers by abstracting them from cloud resource management. However, it does not deal with the application data aspects. As such, developers have to intervene and undergo the burden of managing the application data, often via separate cloud storage services. To further streamline cloud-native application development, in this work, we propose a new paradigm, known as Object as a Service (OaaS) that encapsulates application data and functions into the cloud object abstraction. OaaS relieves developers from resource and data management burden while offering built-in optimization features. Inspired by OOP, OaaS incorporates access modifiers and inheritance into the serverless paradigm that: (a) prevents developers from compromising the system via accidentally accessing underlying data; and (b) enables software reuse in cloud-native application development. Furthermore, OaaS natively supports dataflow semantics. It enables developers to define function workflows while transparently handling data navigation, synchronization, and parallelism issues. To establish the OaaS paradigm, we develop a platform named <italic>Oparaca</i> that offers state abstraction for structured and unstructured data with consistency and fault-tolerant guarantees. We evaluated Oparaca under real-world settings against state-of-the-art platforms with respect to the imposed overhead, scalability, and ease of use. The results demonstrate that the object abstraction provided by OaaS can streamline flexible and scalable cloud-native application development with an insignificant overhead on the underlying serverless system.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"423-434"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Netlist-Independent Functional Stress Pattern Generation Strategy for AI HW Accelerators Embedded into SoCs","authors":"Gabriele Filipponi;Denis Schwachhofer;Francesco Angione;Claudia Bertani;Simone Corbellini;Nicola di Gruttola Giardino;Giuseppe Garozzo;Giorgio Insinga;Vincenzo Tancorre;Paolo Bernardi","doi":"10.1109/TC.2025.3627803","DOIUrl":"https://doi.org/10.1109/TC.2025.3627803","url":null,"abstract":"Artificial Intelligence hardware accelerators are pervading the chip market. Most of the time, they are third-party IPs integrated by silicon manufacturers. As a consequence, their design may be obfuscated, which can introduce issues from a manufacturing testing perspective. This paper illustrates how to effectively and efficiently select the most appropriate functional stress stimuli for Artificial Intelligence (AI) Hardware (HW) Accelerators embedded in System-on-Chip (SoC). The proposed methodology is netlist independent; and it is based on both current measurements from the real chip and architectural evaluations. These ingredients are heuristically used to rank and sift the optimal functional patterns to apply along the Burn-In (BI) phase. Experimental results on two different Automotive SoCs manufactured by STMicroelectronics, demonstrate the effectiveness and efficiency of the proposed method.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"75 2","pages":"554-566"},"PeriodicalIF":4.9,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224013","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148481701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}