An Area Optimization Approach for Large-Scale RM-TB Dual Logic Circuits Based on a Multitasking Optimization Algorithm

Abstract

Logic synthesis is a crucial step in integrated circuit design, and area optimization is an indispensable part of this process. However, the area optimization problem for large-scale Fixed Polarity Reed-Muller (FPRM) circuits is an NP-hard problem. To address this problem, we divide Boolean circuits into small-scale circuits based on the idea of divide-and-conquer using the proposed grouping decomposition mechanism. Each small-scale Boolean circuit is transformed into an FPRM circuit by a polarity transformation algorithm. To ensure the circuit's functionality remains unaffected, we integrate FPRM circuits into an FPRM and Boolean (RM-TB) dual logic circuit based on the proposed gate-level integration. However, the area optimization problem of RM-TB dual logic circuits is a multi-task, high-dimensional, and multi-extremal combinatorial optimization problem. Therefore, we propose a Multipopulation Multitasking Optimization Algorithm (MMuOA) that integrates self-evolution with a multitasking equilibrium optimizer and cross-task evolution through knowledge sharing and transfer. This forms a dynamic optimization framework for simultaneously searching for the optimal polarity corresponding to the minimal area of RM-TB dual logic circuits. Moreover, we propose an Area Optimization Approach (AOA) for an RM-TB dual logic circuit with the minimum area using the MMuOA. Experimental results based on the Microelectronics Center of North Carolina (MCNC) Benchmark test circuits demonstrate the effectiveness and superiority of the AOA compared to the state-of-the-art area optimization approach.