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X-Sources Analysis for Improving the Test Quality 提高测试质量的x源分析
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00031
Kun-Han Tsai
{"title":"X-Sources Analysis for Improving the Test Quality","authors":"Kun-Han Tsai","doi":"10.1109/ITC-ASIA.2018.00031","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00031","url":null,"abstract":"Achieving very high test coverage (e.g. 99.9% stuck-at fault model) is becoming a standard for ICs used in the high reliable systems like automotive vehicle. X-sources (unknown value sources) are one of the common root causes preventing designs from achieving the test coverage goal. The paper first summarizes common X-sources in industry designs. A novel approach is then proposed to systematically identify and analyze all of the X-sources that impacts the test coverage most with accurate estimation by utilizing the Automatic Test Pattern Generator (ATPG). Consequently, users are able to take the analysis result and make necessary and minimum changes to eliminate Xs to achieve the test quality goal effectively.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133256551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run 在一次ATPG运行中生成卡滞故障和转换故障的紧凑测试模式
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00011
Yi-Cheng Kung, Kuen-Jong Lee, S. Reddy
{"title":"Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run","authors":"Yi-Cheng Kung, Kuen-Jong Lee, S. Reddy","doi":"10.1109/ITC-ASIA.2018.00011","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00011","url":null,"abstract":"This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132132052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique 结合布局技术设计一种新型双节点容扰锁闩的辐射硬化
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00019
Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo
{"title":"Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique","authors":"Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo","doi":"10.1109/ITC-ASIA.2018.00019","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00019","url":null,"abstract":"This paper presents a novel double-node upset (DNU) tolerant latch through radiation-hardening-by-design combined with layout technique. The latch mainly comprises 6 interlocked cross-coupled input-split inverters. Due to the special feedback rules for the internal nodes, many interlocked feedback loops are constructed in the latch and the following robustness is achieved: 1) In the case of 0 being held, the latch can self-recover from any single node upset (SNU), any DNU including double-adjacent-node upset (DANU) and double-separated-node upset (DSNU); 2) In the case of 1 being held, the latch can self-recover from any SNU, any DANU and partial DSNU. However, using layout technique, as for any DSNU-sensitive node-pair, the nodes are separated, thus the latch can avoid any DSNU. Simulation results demonstrate the robustness of the proposed latch. Besides, compared with typical existing DNU hardened latch designs, the proposed latch approximately saves 80.25% area-power-delay product on average.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation 针对布局后验证中设置冲突的倾斜感知功能时序分析
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00022
Pin-Ru Jhao, D. Wu, Charles H.-P. Wen
{"title":"Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation","authors":"Pin-Ru Jhao, D. Wu, Charles H.-P. Wen","doi":"10.1109/ITC-ASIA.2018.00022","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00022","url":null,"abstract":"Beyond the deep sub-micron era, clock skew is becoming an indispensable factor in post-layout timing and contributes significant delay during signal propagation in paths. Although Functional Timing Analysis (FTA) can provide accurate timing by identifying functionally false paths, clock skew is not yet considered. Therefore, we are motivated to propose a skew-aware functional-timing-analysis engine (named Sk-FTA) for better post-layout validation of designs. In particular, Sk-FTA can save more cost in checking setup-time violations and filters false alarms. Our experimental results show that given three different clock networks, Sk-FTA induces more accurate delay from removing functionally false paths (e.g. 60% less for s13207 under clock tree 3) when comparing with the skew-aware static timing analysis (Sk-STA). Moreover, Sk-FTA eminently yields fewer setup-time violations than Sk-STA does on benchmark circuits. In particular, for vga lcd, all 512 setup-time violations reported by Sk-STA are proved redundant and thus removed, manifesting the power of Sk-FTA.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124033724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures 通过选择合适的EDT架构优化SoC测试调度的工业案例研究
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00029
Guoliang Li, Henry Zhao, Qinfu Yang, J. Qian, Yu Huang
{"title":"Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures","authors":"Guoliang Li, Henry Zhao, Qinfu Yang, J. Qian, Yu Huang","doi":"10.1109/ITC-ASIA.2018.00029","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00029","url":null,"abstract":"Modern large system-on-chip (SoC) designs typically have hundreds of cores. Each core requires a certain number of input/output test channels. At the chip level, however, the total number of test pins is limited such that all core-level test channels cannot be accessed at the same time. Therefore, hierarchical pattern retargeting is required for SoC test. Test scheduling algorithms can be applied to reduce the total test time. In this paper, we add the EDT architectures as one additional dimension of parameter into the prior test scheduling algorithm. Experimental results based on real case studies show that with the proposed flow, the test time can be further reduced up to approximately 24%.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123570974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions 在基于tile的设计方法中实现面向测试的设计-挑战和解决方案
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00018
Venkat Yellapragada, S. Raman, Banadappa Shivaray, L. Romain, B. Nadeau-Dostie, Martin Keim, J. Cote, Albert S. F. Au, Giri Podichetty, Ashok Anbalan
{"title":"Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions","authors":"Venkat Yellapragada, S. Raman, Banadappa Shivaray, L. Romain, B. Nadeau-Dostie, Martin Keim, J. Cote, Albert S. F. Au, Giri Podichetty, Ashok Anbalan","doi":"10.1109/ITC-ASIA.2018.00018","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00018","url":null,"abstract":"A tile based design methodology consists of developing design blocks that are inserted in design layouts by placing blocks next to each other, making a tile-to-tile connection by abutting corresponding physical signal lines at the border of the tile. Very large systems can be easily and rapidly developed by seamlessly integrating tile elements in the layout. Further, the ease of top-level integration underlines the advantages over a bottom-up approach. However, this tile-based approach is incompatible with traditional DFT tools, which were created to work in accordance with the bottom-up design methodology. This paper outlines some of the obstacles to overcome, to support a truly tile-based DFT methodology. We describe here a working solution for a large production design, underlining a successful implementation of a tile-based Memory Test methodology.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accurate Spectral Testing with Impure Test Stimulus for Multi-tone Test 多音测试用非纯测试刺激的精确频谱测试
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1007/978-3-319-77718-4_7
Yuming Zhuang, Degang Chen
{"title":"Accurate Spectral Testing with Impure Test Stimulus for Multi-tone Test","authors":"Yuming Zhuang, Degang Chen","doi":"10.1007/978-3-319-77718-4_7","DOIUrl":"https://doi.org/10.1007/978-3-319-77718-4_7","url":null,"abstract":"","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"924 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126985014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Grey Zone in Pre-Silicon Hardware Trojan Detection Pre-Silicon硬件木马检测的灰色地带
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00024
Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li
{"title":"Grey Zone in Pre-Silicon Hardware Trojan Detection","authors":"Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li","doi":"10.1109/ITC-ASIA.2018.00024","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00024","url":null,"abstract":"Pre-Silicon hardware Trojan detection has been studied for years. The most popular benchmark circuits are from the Trust-Hub. Their common feature is that the probability of activating hardware Trojans is very low. This leads to a series of machine learning based hardware Trojan detection methods which try to find the nets with low signal probability of 0 or 1. On the other hand, it is considered that, if the probability of activating hardware Trojans is high, these hardware Trojans can be easily found through behaviour simulations or during functional test. This paper explores the \"grey zone\" between these two opposite scenarios: if the activation probability of a hardware Trojan is not low enough for machine learning to detect it and is not high enough for behaviour simulation or functional test to find it, it can escape from detection. Experiments show the existence of such hardware Trojans, and this paper suggests a new set of hardware Trojan benchmark circuits for future study.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126381180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Small Trojan Testing Using Bounded Model Checking 使用有界模型检查的小木马测试
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00025
Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang
{"title":"Small Trojan Testing Using Bounded Model Checking","authors":"Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang","doi":"10.1109/ITC-ASIA.2018.00025","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00025","url":null,"abstract":"With the widely using of VLSI circuits, their security issue has been a critical factor to the security of the modern system. In this paper, we propose a testing method using Bounded Model Checking (BMC) to test the small Trojan that is injected by slightly modifying the original design. First, we implement physical inspection on the training chip set that has the same function but from different sources, and extract suspicious circuit pairs by pairwise comparison on the chips. Second, we use BMC to detect the inconsistent functions on the suspicious circuit pairs. Third, we collects these inconsistent functions as well as their corresponding input sequences into a vulnerability scanner library, and test the other chips using that library. Experimental results show the proposed method can detect the small Trojan in sequential circuits with large sequential depth using an optimized computing time. Furthermore, the method can accurately distinguish small Trojans from circuit optimizations in logic synthesis.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116751662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction 基于rram的神经形态硬件的自修复和纠错提高可靠性
2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00014
Jiaping Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu
{"title":"RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction","authors":"Jiaping Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu","doi":"10.1109/ITC-ASIA.2018.00014","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00014","url":null,"abstract":"Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this paper, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. Evaluation of their influence to the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% or more.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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