2018 IEEE International Test Conference in Asia (ITC-Asia)最新文献

Good Die Prediction Modelling from Limited Test Items 从有限的测试项目中获得良好的模具预测模型

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00030

Takeru Nishimi, Yasuo Sato, S. Kajihara, Yoshiyuki Nakamura

引用次数: 2

Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection 基于隐含的并发错误检测的错误指示信号崩溃

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00032

Chih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh

{"title":"Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection","authors":"Chih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh","doi":"10.1109/ITC-ASIA.2018.00032","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00032","url":null,"abstract":"Implication-based concurrent error detection (CED) has been shown to have promising performance for on-line testing. However, many error indication signals may be required for this CED method, and thus incur much additional interconnection. This would result in not only complicated error checking circuits, but also a large compactor design to process the error indication signals. Both would incur high area overhead. In this paper, we present a collapsing technique that can significantly reduce the total number of required error indication signals for implications. This issue has never been addressed in the literature. We find that equivalence and dominance relationships exist between error indication signals, which are quite helpful for signal reduction. Therefore we develop an efficient algorithm to first identify these relationships, and then make good use of them to merge error indication signals without sacrificing the probability of detecting errors. We also employ 19 ISCAS'85 and ITC'99 benchmark circuits to evaluate the effectiveness of the proposed technique. The results show that 48.48% of error indication signals are reduced by our technique on average. This also leads to 39.23% and 34.52% averaged area overhead reduction to the error checking circuit and the compactor design, respectively.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132374384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cost-Effective High Purity Signal Generator Using Pre-distortion 具有成本效益的高纯度信号发生器使用预失真

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00028

Yuming Zhuang, Degang Chen

{"title":"Cost-Effective High Purity Signal Generator Using Pre-distortion","authors":"Yuming Zhuang, Degang Chen","doi":"10.1109/ITC-ASIA.2018.00028","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00028","url":null,"abstract":"sine waves are among the most widely used signals in many applications such as signal and device testing, measurement, communications, medical electronics, consumer electronics, etc. The high purity sine wave is crucial, as it is needed for high precision applications. Such high purity signals have become more challenging to generate, as the devices under test such as Analog-to-Digital Converters (ADCs) performances are becoming better, which the test signals need to have even better performances. This paper presents a cost-effective method to generate high purity sine waves using a nonlinear DAC. Based on a novel method that identifies the DAC nonlinearity, such information is fed back to the DAC input codes, cancels its nonlinearity, and results in a much better purity sine wave output. In addition, both linearity information of the DAC and ADC used can be accurately tested, which can be used for co-testing of the DAC and ADC. Extensive simulation results have verified the functionality and robustness of the proposed method, with different performances, structures or resolutions of the DACs and ADCs. The proposed method and system can be implemented on board or on chip that serves high performance high precision applications, with much lower design requirement and cost.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126373170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors 利用DRAM刷新保护云芯片多处理器的内存时序通道

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00023

Ying Wang, Wen Li, Huawei Li, Xiaowei Li

{"title":"Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors","authors":"Ying Wang, Wen Li, Huawei Li, Xiaowei Li","doi":"10.1109/ITC-ASIA.2018.00023","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00023","url":null,"abstract":"The shared memory controllers of single-chip cloud computing (SCC) processors are vulnerable to timing-channel attacks. Existing protection strategies based on fixed memory bandwidth assignment degrade processor performance and severely harm the experience of cloud-users. This paper proposes a novel light-weight timing channel protection scheme against both side channel and covert channel attacks to the shared memory controllers of cloud chip multi-processors (CMPs). Instead of enforcing a fixed time-slot assignment to the applications, we go an entirely different technical route and utilize the background DRAM refresh as a free noise source to eliminate the time correlation between victim and attacker applications. The proposed protection framework, MemJam, relies on the emerging fine-grained refresh technology to achieve the effects of timing channel obfuscation. Multi-programmed workloads running in a cloud CMP were used to evaluate the protection method. The results show that the light-weight refresh-based noise can effectively block the timing-channel between user applications, and achieve up to 1.61~2.49X memory performance boost compared to prior solutions.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122188961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Distortion One-Tone and Two-Tone Signal Generation Using AWG Over Full Nyquist Region 利用全奈奎斯特区域上的AWG产生低失真单音和双音信号

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00026

Tomonori Yanagida, S. Shibuya, K. Machida, Koji Asami, Haruo Kobayashi

引用次数: 0

Balancing Testability and Security by Configurable Partial Scan Design 可配置部分扫描设计平衡可测试性和安全性

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00035

Xi Chen, Omid Aramoon, G. Qu, Aijiao Cui

{"title":"Balancing Testability and Security by Configurable Partial Scan Design","authors":"Xi Chen, Omid Aramoon, G. Qu, Aijiao Cui","doi":"10.1109/ITC-ASIA.2018.00035","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00035","url":null,"abstract":"Scan chain design facilitates chip testing by providing an interface for the test engineers to access and control the internal states of the circuit. This feature has also been exploited to break systems such as the cryptographic chips by the attack known as scan chain side channel analysis. From the perspective of information access, test engineers and scan chain attackers have the same goal – observe and control the scan chain side channel information. Consequently, all the existing countermeasures have to make the tradeoff between scan chain security and the testability it can provide. In this paper, we propose a novel public-private partial scan chain design which can deliver both full testability and security. The key idea is to partition the flip flops into a public partial chain and a set of parallel private partial chains. The private partial chains are protected by means of a hardware implemented finite state machine and an obfuscation mechanism based on configurable physical unclonable function. We demonstrate how full testability can be achieved by the proposed public-private partial chains. We conduct security and performance analysis to show that our approach is robust against all the known scan chain based attacks and can improve testing time and power consumption with negligible hardware overhead.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System 基于pim的异构计算系统mttf感知可靠性任务调度

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00015

Desong Pang, Dawen Xu, Ying Wang, Huaguo Liang

引用次数: 0

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers 设计区域高效并发在线检查器的分层方法

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00034

Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, J. Raik, G. Jervan

{"title":"A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers","authors":"Behrad Niazmand, Siavoosh Payandeh Azad, Tara Ghasempouri, J. Raik, G. Jervan","doi":"10.1109/ITC-ASIA.2018.00034","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00034","url":null,"abstract":"The shrinking feature size in semiconductor technology beyond the sub-micron domain negatively affects the reliability of digital circuits and makes them more susceptible to run-time faults (such as wear-out and aging) and transient faults during systems life time. This motivates investigation of online faults detection approaches, which would react instantaneously at run-time, concurrent with the system operation. Concurrent online checkers have been one of the approaches introduced in the literature for handling run-time faults online in control part of digital systems. An ideal set of checkers provides high fault detection and localization with minimal area overhead. To reach such optimal set, a diverse initial set of checkers are required which provide a trade-off between the above mentioned parameters. This work presents a methodology to generate (1) high-level functional checkers based on abstract design specification, and (2) structural checkers, which are devised from Register Transfer Level (RTL) description of the circuit. The functional checkers are fewer in number with lower area overhead and provide high fault coverage, however they lead to lower fault localization accuracy and cannot cover all the Single Event Upsets (SEUs). On the other hand, structural checkers provide higher localization accuracy and guarantee 100% SEU coverage, but at the price of higher area overhead. The proposed methodology provides the designer with trade-offs between the parameters mentioned above, for further optimization. The proposed methodology has been applied to the control part of routing logic of a NoC router.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116350957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks 生成可重构扫描网络有效测试序列的半形式化技术

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00020

R. Cantoro, A. Damljanovic, M. Reorda, Giovanni Squillero

{"title":"A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks","authors":"R. Cantoro, A. Damljanovic, M. Reorda, Giovanni Squillero","doi":"10.1109/ITC-ASIA.2018.00020","DOIUrl":"https://doi.org/10.1109/ITC-ASIA.2018.00020","url":null,"abstract":"The broad need to efficiently access all the instrumentation embedded within a semiconductor device called for a standardization, and the reconfigurable scan networks proposed in IEEE 1687 have been demonstrated effective in handling complex infrastructures. At the same time, different techniques have been proposed to test the new circuitry required; however, most of the automatic approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper models the state of a reconfigurable scan network with a finite state automaton, using the length of the active path as the output alphabet and the configurations as input symbols. Permanent faults are represented as incorrect transitions, and a greedy algorithm is used to generate a functional test sequence able to detect all these multiple state-transition faults. The automaton's state set and the input alphabet are small subsets of the possible ones, and are carefully chosen. Experimental results on ITC'16 benchmarks demonstrate that the proposed approach is broadly applicable; the test sequences are more efficient than the ones previously generated by search heuristics.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121659457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Periodic Online LBIST Considerations for a Multicore Processor 多核处理器的周期性在线LBIST考虑

2018 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2018-08-01 DOI: 10.1109/ITC-ASIA.2018.00017

T. McLaurin

引用次数: 9