A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers

Abstract

The shrinking feature size in semiconductor technology beyond the sub-micron domain negatively affects the reliability of digital circuits and makes them more susceptible to run-time faults (such as wear-out and aging) and transient faults during systems life time. This motivates investigation of online faults detection approaches, which would react instantaneously at run-time, concurrent with the system operation. Concurrent online checkers have been one of the approaches introduced in the literature for handling run-time faults online in control part of digital systems. An ideal set of checkers provides high fault detection and localization with minimal area overhead. To reach such optimal set, a diverse initial set of checkers are required which provide a trade-off between the above mentioned parameters. This work presents a methodology to generate (1) high-level functional checkers based on abstract design specification, and (2) structural checkers, which are devised from Register Transfer Level (RTL) description of the circuit. The functional checkers are fewer in number with lower area overhead and provide high fault coverage, however they lead to lower fault localization accuracy and cannot cover all the Single Event Upsets (SEUs). On the other hand, structural checkers provide higher localization accuracy and guarantee 100% SEU coverage, but at the price of higher area overhead. The proposed methodology provides the designer with trade-offs between the parameters mentioned above, for further optimization. The proposed methodology has been applied to the control part of routing logic of a NoC router.