{"title":"结合布局技术设计一种新型双节点容扰锁闩的辐射硬化","authors":"Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo","doi":"10.1109/ITC-ASIA.2018.00019","DOIUrl":null,"url":null,"abstract":"This paper presents a novel double-node upset (DNU) tolerant latch through radiation-hardening-by-design combined with layout technique. The latch mainly comprises 6 interlocked cross-coupled input-split inverters. Due to the special feedback rules for the internal nodes, many interlocked feedback loops are constructed in the latch and the following robustness is achieved: 1) In the case of 0 being held, the latch can self-recover from any single node upset (SNU), any DNU including double-adjacent-node upset (DANU) and double-separated-node upset (DSNU); 2) In the case of 1 being held, the latch can self-recover from any SNU, any DANU and partial DSNU. However, using layout technique, as for any DSNU-sensitive node-pair, the nodes are separated, thus the latch can avoid any DSNU. Simulation results demonstrate the robustness of the proposed latch. Besides, compared with typical existing DNU hardened latch designs, the proposed latch approximately saves 80.25% area-power-delay product on average.","PeriodicalId":129553,"journal":{"name":"2018 IEEE International Test Conference in Asia (ITC-Asia)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique\",\"authors\":\"Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo\",\"doi\":\"10.1109/ITC-ASIA.2018.00019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel double-node upset (DNU) tolerant latch through radiation-hardening-by-design combined with layout technique. The latch mainly comprises 6 interlocked cross-coupled input-split inverters. Due to the special feedback rules for the internal nodes, many interlocked feedback loops are constructed in the latch and the following robustness is achieved: 1) In the case of 0 being held, the latch can self-recover from any single node upset (SNU), any DNU including double-adjacent-node upset (DANU) and double-separated-node upset (DSNU); 2) In the case of 1 being held, the latch can self-recover from any SNU, any DANU and partial DSNU. However, using layout technique, as for any DSNU-sensitive node-pair, the nodes are separated, thus the latch can avoid any DSNU. Simulation results demonstrate the robustness of the proposed latch. Besides, compared with typical existing DNU hardened latch designs, the proposed latch approximately saves 80.25% area-power-delay product on average.\",\"PeriodicalId\":129553,\"journal\":{\"name\":\"2018 IEEE International Test Conference in Asia (ITC-Asia)\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Test Conference in Asia (ITC-Asia)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITC-ASIA.2018.00019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Test Conference in Asia (ITC-Asia)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITC-ASIA.2018.00019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique
This paper presents a novel double-node upset (DNU) tolerant latch through radiation-hardening-by-design combined with layout technique. The latch mainly comprises 6 interlocked cross-coupled input-split inverters. Due to the special feedback rules for the internal nodes, many interlocked feedback loops are constructed in the latch and the following robustness is achieved: 1) In the case of 0 being held, the latch can self-recover from any single node upset (SNU), any DNU including double-adjacent-node upset (DANU) and double-separated-node upset (DSNU); 2) In the case of 1 being held, the latch can self-recover from any SNU, any DANU and partial DSNU. However, using layout technique, as for any DSNU-sensitive node-pair, the nodes are separated, thus the latch can avoid any DSNU. Simulation results demonstrate the robustness of the proposed latch. Besides, compared with typical existing DNU hardened latch designs, the proposed latch approximately saves 80.25% area-power-delay product on average.