2020 23rd Euromicro Conference on Digital System Design (DSD)最新文献_第6页

Dynamic encoding, a lightweight combined countermeasure against hardware attacks 动态编码，一种轻量级的对抗硬件攻击的组合对策

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00039

Maxime Montoya, Simone Bacles-Min, A. Molnos, J. Fournier

{"title":"Dynamic encoding, a lightweight combined countermeasure against hardware attacks","authors":"Maxime Montoya, Simone Bacles-Min, A. Molnos, J. Fournier","doi":"10.1109/DSD51259.2020.00039","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00039","url":null,"abstract":"With the Internet of Things (IoT) an increasing amount of sensitive data have to be communicated and hence encrypted. Low-cost hardware attacks such as fault analysis (FA) or side-channel analysis (SCA) threaten the implementation of cryptographic algorithms. Many countermeasures have been proposed against either of these attacks, however, only a few countermeasures protect efficiently an implementation against both attacks. These combined countermeasures usually have a prohibitive area and power overhead, and require up to thousands of bits of fresh randomness at each encryption. Therefore, they may not be suited to protect lightweight algorithms in resource-constrained devices. In this paper, we propose a new combined countermeasure, which is particularly adapted to protect lightweight algorithms based on shift registers. It achieves an efficient power balancing at algorithmic level, and provides an inherent fault detection with a better coverage than most existing combined countermeasures. Furthermore, it has a smaller power and area overhead than existing combined countermeasures, and requires at most 8 random bits at each encryption.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"134 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Active Implant to Restore Dental Proprioceptivity 一种恢复牙齿本体感觉的主动种植体

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00058

J. M. D. Silva, Ilaria Cerrone, Daniel Malágon, Jorge Marinho, Stephen Mundy, João Gaspar, J. Mendes

引用次数: 1

Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation fpga中近似TMR可靠性与缓解成本的权衡

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00107

Umar Afzaal, Jeong-A Lee

{"title":"Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation","authors":"Umar Afzaal, Jeong-A Lee","doi":"10.1109/DSD51259.2020.00107","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00107","url":null,"abstract":"A number of works have focused on relaxing circuit specification for building partial TMR circuits, but a framework for analysing the effect of circuit degradation on its dependability is missing in the literature. This paper aims to bridge this gap by developing a reliability model for approximate TMR circuits implemented in FPGAs and the parameter definitions for controlling design trade-offs with reliability in the approximation process. The framework is useful in the assignment of the design parameters such that the reliability constraints of the application at hand are satisfied. Reliability curves for different trade-offs show a sharp decline in reliability even at small error thresholds, requiring that for maintaining system operation in the high reliability region, a TMR approximation method must achieve the desired reduction in hardware overheads within tight error constraints. Furthermore, the effect of an unprotected voter on the overall system reliability is also quantified. To which end, it is shown that the simple unprotected voter results in significant degradation on the approximate TMR reliability and therefore using a fault-tolerant voting circuit is essential to a reliable system operation.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128426778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

MPU-based incremental checkpointing for transiently-powered systems 基于微处理器的暂态供电系统增量检查点

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00025

Gautier Berthou, K. Marquet, T. Risset, Guillaume Salagnac

引用次数: 2

Intrusion Detection for SOME/IP: Challenges and Opportunities 针对某些/IP的入侵检测:挑战与机遇

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00096

Tobias Gehrmann, P. Duplys

引用次数: 13

Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks RRAM单元对光故障注入攻击的敏感性评估

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00047

D. Petryk, Z. Dyka, E. Pérez, Mamathamba Kalishettyhalli Mahadevaiaha, I. Kabin, C. Wenger, P. Langendörfer

引用次数: 3

Classification-Based Unified Cache Replacement via Partitioned Victim Address History 基于分类的统一缓存替换通过分区受害者地址历史

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00027

Eishi Arima

{"title":"Classification-Based Unified Cache Replacement via Partitioned Victim Address History","authors":"Eishi Arima","doi":"10.1109/DSD51259.2020.00027","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00027","url":null,"abstract":"In modern microprocessors, lower level cache memories are usually implemented as unified caches where different classes of cachelines such as data, instructions, and Page Table Entries (PTEs) coexist. Particularly, frequent PTE accesses following after TLB missies can happen on modern systems, which is driven by the increasing demands of applications for larger working set size, and this trend naturally leads to significant conflicts among these different kinds of cachelines.This paper targets the emerging conflict problem and provides a systematic mechanism using a partitioned victim address history. Prior studies have shown the effectiveness of history-based cache managements to predict the reuseness and thus to improve the hit rate. This work augments the following functionalities: (1) partitioning the history into multiple areas to separately keep track of the reuseness for all the different cacheline categories; and (2) setting different allocation priorities to the different cacheline categories when cache replacement. Furthermore, this paper proposes a control system to dynamically optimize the history partitions and the cache allocation priorities at the same time by using the statistics of the history structure. The experimental result indicates that the proposed technique improves performance considerably compared with the conventional LRU-based approach and others.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126466358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy-Optimized Elastic Application Distribution for Automotive Systems in Hybrid Cloud Architectures 混合云架构下汽车系统能量优化弹性应用分布

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00078

Philipp Weber, Philipp Weiss, Dominik Reinhardt, S. Steinhorst

{"title":"Energy-Optimized Elastic Application Distribution for Automotive Systems in Hybrid Cloud Architectures","authors":"Philipp Weber, Philipp Weiss, Dominik Reinhardt, S. Steinhorst","doi":"10.1109/DSD51259.2020.00078","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00078","url":null,"abstract":"The increase of resource-intensive applications in modern vehicles used for streaming, gaming or autonomous driving results in rising energy-consumption of its advanced computing and connectivity hardware. Especially in electric vehicles, this leads to much higher hardware costs and a decreased vehicle range. Modern premium cars use distributed heterogeneous hardware and mostly communicate via APIs to large cloud backends. Current approaches to reduce on-board energy consumption offload applications partly and make use of limited network connectivity assumptions to their backends. In this paper, we propose a hybrid electric and electronic architecture that manages vehicle hardware by using cloud computing frameworks. Our hybrid cloud architecture is a connection of the local vehicle cloud and a large data centre community cloud. We propose an online optimization algorithm that shifts applications from on-board ECUs to data centre servers and vice-versa. The optimization algorithm minimizes the local energy-consumption while satisfying predicatively dynamic constraints like data rate limitations, application policies and resource limitations. Our approach outperforms the non-predictive approach in average by 16%, in the best case by 21% and in the worst case both behave equally well.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117267152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Pipelined ALU for effective external memory access in FPGA 流水线ALU在FPGA中有效的外部存储器访问

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00026

Tomás Benes, Michal Kekely, Karel Hynek, T. Čejka

引用次数: 1

Online GPUAnalysis using Adaptive DMA Controlled by Softcore for 2D Detectors 利用Softcore控制的自适应DMA对二维探测器进行在线gpu分析

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00075

Raphael Ponsard, N. Janvier, D. Houzet, V. Fristot, W. Mansour

引用次数: 2