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2020 23rd Euromicro Conference on Digital System Design (DSD)最新文献

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Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout 量子和可逆电路的几何重构:量子布局
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00074
M. Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze
{"title":"Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout","authors":"M. Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze","doi":"10.1109/DSD51259.2020.00074","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00074","url":null,"abstract":"With the advent of gated quantum computers and regular structures of the qubit layout, methods for placement, routing, noise estimation and logic to hardware mapping become imminently required. In this paper, we propose a method for quantum circuit layout that is intended to solve such problems when mapping a quantum circuit to a quantum computer. The proposed method starts by building a Circuit Interaction Graph (CIG) that represents the ideal hardware layout minimizing the distance and path length between the individual qubits. The CIG is also used to introduce a qubit noise model. Once constructed, the CIG is iteratively reduced to a given architecture (qubit coupling model) specifying the neighborhood, qubits, priority and qubits noise. The introduced constraints allow to additionally reduce the graph according to preferred weights of desired properties. The proposed method is verified and tested on a set of standard benchmarks.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115167380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow 基于组件的嵌入式系统设计流程的运行时监控和跟踪分析方法
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00029
V. Muttillo, G. Valente, L. Pomante, H. Posadas, Javier Merino, E. Villar
{"title":"Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow","authors":"V. Muttillo, G. Valente, L. Pomante, H. Posadas, Javier Merino, E. Villar","doi":"10.1109/DSD51259.2020.00029","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00029","url":null,"abstract":"The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"63 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic State Space Analysis for Modeling Untrusted Embedded Device Drivers 不可信嵌入式设备驱动程序建模的自动状态空间分析
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00028
Thomas Fehmel, Viet-Tan Nguyen, D. Stoffel, W. Kunz
{"title":"Automatic State Space Analysis for Modeling Untrusted Embedded Device Drivers","authors":"Thomas Fehmel, Viet-Tan Nguyen, D. Stoffel, W. Kunz","doi":"10.1109/DSD51259.2020.00028","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00028","url":null,"abstract":"This paper presents a semi-automatic methodology to create abstract driver models to be used as formal reference when developing the firmware for embedded device drivers. Our methodology extracts the behavior of driver software automatically as an abstract finite state machine. This replaces manually crafting these models from informal specifications, which is error-prone, laborious, and does not account for undocumented behavior. Our approach specifically targets untrusted driver software that is only available as binary code, for example as third-party IP, and for which the source code is unknown. Our extracted model is formally sound with respect to the implementation, while still being understandable by a human developer. Our experiments for industry-size driver software demonstrate that human-readable, sound, abstract driver models can be extracted from binary code in affordable run times and with small manual effort.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114855733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks 用于非连续运行时钟的无故障时钟多路复用器
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00013
Steffen Zeidler, O. Schrape, A. Breitenreiter, M. Krstic
{"title":"A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks","authors":"Steffen Zeidler, O. Schrape, A. Breitenreiter, M. Krstic","doi":"10.1109/DSD51259.2020.00013","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00013","url":null,"abstract":"Modern system-on-chips often integrate blocks, which need to be triggered by two or more clock sources depending on the circuit state. Glitchfree clock multiplexers are introduced to such systems for selecting the demanded clock. One specific problem of state-of-the-art solutions is that they need running clocks to perform the switching from one to another source. In this paper, a new clock multiplexer is presented, which overcomes this limitation and enables switching the clock, even if the clock stops running before switching has been performed. The applicability of the multiplexer has been proven in silicon by integrating it into a radhard 1.6-2.5 Gbps SERDES for space applications.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip 自适应低功耗和容错片上系统的高度可配置框架
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00015
M. Veleski, M. Hübner, M. Krstic, R. Kraemer
{"title":"Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip","authors":"M. Veleski, M. Hübner, M. Krstic, R. Kraemer","doi":"10.1109/DSD51259.2020.00015","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00015","url":null,"abstract":"In this paper, a novel, highly configurable framework for low power and error-resilient System-On-Chip is presented. The framework is composed, on the one hand, of the SWIELD configurable flip-flop and on the other hand, of the Chameleon controller. The SWIELD flip-flop is able to operate in three modes. It is driven/configured during runtime via the dedicated controller called Chameleon System Operation Management Unit. The proposed framework is integrated into a complex SoC based on a 32-bit general-purpose processor and the entire system is synthesized using the IHP $130 nm$ technology library. Numerous simulation experiments have been conducted in order to estimate the system error resilience and power consumption. At expense of negligible area and complexity overhead, the introduced framework shows great potential and excellent results w.r.t. both metrics of interest.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126096075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration μ-Genie:内存感知空间处理器架构协同设计探索的框架
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00038
Giulio Stramondo, M. Gomony, B. Kozicki, C. D. Laat, A. Varbanescu
{"title":"μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration","authors":"Giulio Stramondo, M. Gomony, B. Kozicki, C. D. Laat, A. Varbanescu","doi":"10.1109/DSD51259.2020.00038","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00038","url":null,"abstract":"Spatial processor architectures are essential to meet the increasing demand in performance and energy efficiency of both embedded and high performance computing systems. Due to the growing performance gap between memories and processors, the memory system of ten determines the overall performance and power consumption in silicon. The interdependency between memory system and spatial processor architectures suggests that they should be co-designed. For the same reason, state-of-the-art design methodologies for processor architectures are ineffective for spatial processor architectures because they do not include the memory system. In this paper, we present μ -Genie: an automated framework for co-design-space exploration of spatial processor architecture and the memory system, starting from an application description in a high-level programming language. In addition, we propose a spatial processor architecture template that can be configured at design-time for optimal hardware implementation. To demonstrate the effectiveness of our approach, we show a case study of co-designing a spatial processor using different memory technologies.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Assuring the Safety of End-to-End Learning-Based Autonomous Driving through Runtime Monitoring 通过运行时监控确保端到端学习自动驾驶的安全性
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00081
J. Grieser, Meng Zhang, Tim Warnecke, A. Rausch
{"title":"Assuring the Safety of End-to-End Learning-Based Autonomous Driving through Runtime Monitoring","authors":"J. Grieser, Meng Zhang, Tim Warnecke, A. Rausch","doi":"10.1109/DSD51259.2020.00081","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00081","url":null,"abstract":"Artificial intelligence is a promising element in the development of autonomous vehicles. We have designed an end-to-end learning-based autonomous driving system solely with a neural network through supervised learning, which has been deployed on a model vehicle equipped with a lidar. Input of the convolutional neural network are the point clouds from the lidar and outputs are the requested drive torques and steering angles. For the training of the neural network, the required sensor and actuator data were recorded by remotely controlling the model vehicle. With supervised learning, the end-to-end neural network learns the safety-relevant rules only implicitly through examples in the training data. Because it is not guaranteed that the neural network has learned all necessary rules and can apply them correctly in all situations, safe operation cannot be assured. To address this safety issue, we developed a software architecture including a runtime monitoring component. If the runtime monitoring component detects a violation of any predefined safety rule, it will select an appropriate strategy in order to transfer the vehicle into a safe state.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"18 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Comparison of Approximate Circuits for H.264 and HEVC Motion Estimation H.264和HEVC运动估计近似电路的比较
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00036
Waqar Ahmad, Berke Ayrancioglu, Ilker Hamzaoglu
{"title":"Comparison of Approximate Circuits for H.264 and HEVC Motion Estimation","authors":"Waqar Ahmad, Berke Ayrancioglu, Ilker Hamzaoglu","doi":"10.1109/DSD51259.2020.00036","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00036","url":null,"abstract":"Motion estimation is the most computationally complex and power consuming module in video encoder hardware. Approximate hardware can achieve better performance, area and power consumption than accurate hardware while providing acceptable quality for error tolerant applications. In this paper, an approximate adder is proposed. Detailed comparison of several approximate circuits including the proposed approximate adder and traditional bit truncation technique for H.264 and HEVC motion estimation is presented. The proposed approximate adder achieved up to 10% power reduction in motion estimation hardware while providing better quality than the other approximate circuits.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122757603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors 微处理器转换延迟故障的实现无关功能测试
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00105
Adeboye Stephen Oyeniran, R. Ubar, M. Jenihhin, J. Raik
{"title":"Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors","authors":"Adeboye Stephen Oyeniran, R. Ubar, M. Jenihhin, J. Raik","doi":"10.1109/DSD51259.2020.00105","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00105","url":null,"abstract":"We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121512679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
DSD 2020 TOC
2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/dsd51259.2020.00004
Humberto Carvalho, Geoffrey Nelissen, Tomáš Beneš
{"title":"DSD 2020 TOC","authors":"Humberto Carvalho, Geoffrey Nelissen, Tomáš Beneš","doi":"10.1109/dsd51259.2020.00004","DOIUrl":"https://doi.org/10.1109/dsd51259.2020.00004","url":null,"abstract":"","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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