2020 23rd Euromicro Conference on Digital System Design (DSD)最新文献_第4页

A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA 基于FPGA的多尺度色度保持视网膜的硬件结构

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00023

Jorge Andrés Palacios, Vincenzo Caro, Miguel Durán, M. Figueroa

{"title":"A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA","authors":"Jorge Andrés Palacios, Vincenzo Caro, Miguel Durán, M. Figueroa","doi":"10.1109/DSD51259.2020.00023","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00023","url":null,"abstract":"Image-processing algorithms based on Retinex theory aim to model human color perception to enhance images with low contrast or poor illumination. In particular, the Multiscale Retinex with Chromacity Preservation (MSRCP) algorithm improves on the original Retinex by processing the image at multiple scales and adding a color balance step in postprocessing. Despite their advantages, multiscale Retinex algorithms are computationally intensive, and real-time video processing is not generally possible with general-purpose processor architectures. In this paper, we present a special-purpose hardware accelerator for the MSRCP algorithm. The accelerator introduces tradeoffs to the original formulation of MSRCP by reducing the magnitude of the scales and using a cumulative histogram in the colorbalance stage. Despite these modifications, we show that the accelerator produces images that are visually almost identical to a software implementation of the original MSRCP algorithm. We implement our design on a Xilinx XC7A200T-1SBG484C FPGA, which is capable of processing $1280times 720$-pixel video at up to 94 frames per second, a speedup of 123x compared to a desktop computer running a software version of the algorithm.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A hardware accelerator for entropy estimation using the top-k most frequent elements 一个使用top-k最频繁元素进行熵估计的硬件加速器

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00032

Javier E. Soto, Paulo Ubisse, Cecilia Hernández, M. Figueroa

{"title":"A hardware accelerator for entropy estimation using the top-k most frequent elements","authors":"Javier E. Soto, Paulo Ubisse, Cecilia Hernández, M. Figueroa","doi":"10.1109/DSD51259.2020.00032","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00032","url":null,"abstract":"Estimating the empirical entropy of the elements in a dataset is an important task in data analysis. In particular, empirical entropy can be effectively used to detect anomalies in network traffic. However, computing the empirical entropy of a large dataset is computationally expensive and requires a large amount of memory. This is particularly important in high-speed network traffic analysis, where computing the entropy of a data flow in real time requires using hardware accelerators with restricted on-chip memory and arithmetic resources. In this work, we propose a method to estimate the entropy using a streaming algorithm with sublinear space requirements. Our approach uses a sketch to estimate the frequency of the elements in the stream, and a priority queue to store the top-k most frequent elements. We show that our method can provide a good approximation of the entropy of the dataset, and present the design of a hardware accelerator that can compute the entropy of the stream with a throughput of one packet per clock cycle. Implemented on a Xilinx Zynq UltraScale + MPSoC ZCU102 FPGA, our accelerator can operate at line rates above 181 Gbps, consuming 511 mW and using less than 24% of the resources available on the device.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125223411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems 固有冗余故障操作系统的成本高效容错方法

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00103

Tobias Dörr, T. Sandmann, Patrick Friederich, Arnd Leitner, J. Becker

{"title":"An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems","authors":"Tobias Dörr, T. Sandmann, Patrick Friederich, Arnd Leitner, J. Becker","doi":"10.1109/DSD51259.2020.00103","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00103","url":null,"abstract":"Embedded systems in safety-critical environments are often subject to strict reliability requirements. This holds particularly true for modern fail-operational systems. In order to deliver a guaranteed minimum functionality at all times, these systems are often based on expensive fault tolerance mechanisms. In this work, we consider fail-operational systems with inherent redundancy. This property describes the presence of multiple hardware components, each of which is underutilized to a certain degree and thus able to serve as a fallback for one of the other components. We propose an off-chip fault tolerance mechanism for a pair of inherently redundant execution units that requires no further replication of these expensive resources. The key component of this concept is a lightweight proxy unit that handles faults of one execution unit by dynamically migrating the safety-critical portion of its functionality to its redundant counterpart. We present a prototypical implementation of this concept and evaluate the fault handling time of the resulting system experimentally. The results show that for an exemplary, processor-based control system with 256 bits of internal state, a cycle time of four milliseconds, and 64 bits of payload data that are read from or written to attached devices per cycle, the presented implementation is able to detect the failure of a unit, activate a fallback functionality on the complementary unit, and restore the internal state variables within five milliseconds.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125312119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Lightweight Blockchain-based Technique for Anti-Tampering in Wireless Sensor Networks 基于区块链的无线传感器网络防篡改技术

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00095

Walter Tiberti, A. Carmenini, L. Pomante, D. Cassioli

引用次数: 6

UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems 更新日期:对高性能混合临界系统进行安全可靠的无线软件更新

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00063

Irune Agirre, P. Onaindia, Tomaso Poggi, Irune Yarza, F. Cazorla, Leonidas Kosmidis, Kim Grüttner, M. Abuteir, Jan Loewe, Juan M. Orbegozo, Stefania Botta

{"title":"UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems","authors":"Irune Agirre, P. Onaindia, Tomaso Poggi, Irune Yarza, F. Cazorla, Leonidas Kosmidis, Kim Grüttner, M. Abuteir, Jan Loewe, Juan M. Orbegozo, Stefania Botta","doi":"10.1109/DSD51259.2020.00063","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00063","url":null,"abstract":"Following the same trend of consumer electronics, safety-critical industries are starting to adopt Over-The-Air Software Updates (OTASU) on their embedded systems. The motivation behind this trend is twofold. On the one hand, OTASU offer several benefits to the product makers and users by improving or adding new functionality and services to the product without a complete redesign. On the other hand, the increasing connectivity trend makes OTASU a crucial cyber-security demand to download latest security patches. However, the application of OTASU in the safety-critical domain is not free of challenges, specially when considering the dramatic increase of software complexity and the resulting high computing performance demands. This is the mission of UP2DATE, a recently launched project funded within the European H2020 programme focused on new software update architectures for heterogeneous high-performance mixed-criticality systems. This paper gives an overview of UP2DATE and its foundations, which seeks to improve existing OTASU solutions by considering safety, security and availability from the ground up in an architecture that builds around composability and modularity.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129277662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Adjustable self-healing methodology for accelerated functions in heterogeneous systems 异构系统中加速函数的可调自愈方法

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00104

M. Riazati, Tara Ghasempouri, M. Daneshtalab, J. Raik, Mikael Sjödin, B. Lisper

{"title":"Adjustable self-healing methodology for accelerated functions in heterogeneous systems","authors":"M. Riazati, Tara Ghasempouri, M. Daneshtalab, J. Raik, Mikael Sjödin, B. Lisper","doi":"10.1109/DSD51259.2020.00104","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00104","url":null,"abstract":"Self-healing is a promising approach for designing reliable digital systems. It refers to the ability of a system to detect faults and automatically fixing them to avoid total failure. With the development of digital systems, heterogeneous systems, in which some parts of the system are executed on the programmable logic, and some other parts run on the processing elements (CPU), are becoming more prevalent. In this work, we propose an adjustable self-healing method that is applicable to heterogeneous systems with accelerated functions and enables the designers to add the self-healing feature to the design. In this method, by manipulating the software codes that are being executed on the processing element, we add the ability to verify the accelerated functions on the programmable logic and heal the possible failures to the system. This is done not only in a straightforward manner but also without being forced to choose a specific reliability-overhead point. The designer will have the option to select the optimum configuration for a desired reliability level. Experimental results on a large design including several accelerated functions are provided and show 42% improvement of reliability by having 27% overhead, as an example of the reliability-overhead point.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129757065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Crop Type Classification based on Machine Learning with Multitemporal Sentinel-1 Data 基于multi - temporal Sentinel-1数据的机器学习作物类型分类

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00092

J. Jeppesen, R. Jacobsen, R. Jørgensen

{"title":"Crop Type Classification based on Machine Learning with Multitemporal Sentinel-1 Data","authors":"J. Jeppesen, R. Jacobsen, R. Jørgensen","doi":"10.1109/DSD51259.2020.00092","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00092","url":null,"abstract":"The amount of open satellite data has increased tremendously in recent years, simultaneously with a continuing decrease in the price of high performance cloud computing. This can be combined with machine learning methods to perform crop type classification in the agricultural sector. In this paper, we propose a data processing chain for processing multitemporal Sentinel-1 SAR data, and show how the temporal patterns of agricultural fields can be visualized to provide a valuable overview prior to classification. We then investigate the performance of 6 machine learning methods for crop type classification of 12 crop types based on 44333 fields, and achieve an overall accuracy of (94.02 ± 0.25)% with an RBF SVM classifier. The dataset used is a subset of all the fields of the chosen crop types in Denmark in 2019, which comprises a total of 289810, or 49.34% of all fields in the country for the 2019 season. The entire data processing chain is based on open data and free open source software, thereby minimizing the cost of practical applications and future work for both industry and academia. All code used for the paper is available on GitHub.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats 立方体卫星容错在线调度算法的评估

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00102

Petr Dobiáš, Emmanuel Casseau, O. Sinnen

引用次数: 0

Toward unsupervised Human Activity Recognition on Microcontroller Units 基于单片机的无监督人体活动识别研究

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00090

Pierre-Emmanuel Novac, A. Castagnetti, A. Russo, Benoît Miramond, A. Pegatoquet, F. Verdier

{"title":"Toward unsupervised Human Activity Recognition on Microcontroller Units","authors":"Pierre-Emmanuel Novac, A. Castagnetti, A. Russo, Benoît Miramond, A. Pegatoquet, F. Verdier","doi":"10.1109/DSD51259.2020.00090","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00090","url":null,"abstract":"Bringing artificial intelligence to embedded devices has become a central research topic in many scientific domains (environment, agriculture, sociology, health…). For Human Activity Recognition, Artificial Neural Networks (ANNs) have shown their capability to provide better performance compared to other machine learning methods. However, ANNs suffer from two major limitations. First, ANNs are often trained using supervised learning requiring labelled databases, which are often difficult to build in real applications. Then, those algorithms are usually very expensive in terms of computing power. For that reason, their integration into low-power microcontrollers has been so far only evaluated to a limited extent. In this paper, we propose to evaluate quantitatively and qualitatively the embedded implementation of different neural networks for human activity recognition. First, supervised learning approaches are presented, followed by an exploratory study of unsupervised learning approaches using Self-Organizing Maps. Finally, some aspects of embedded unsupervised online learning are investigated to improve classification results using subject-specific data over a more general training. Each neural network is tested on a Human Activity Recognition dataset acquired from a smartphone using accelerometer and gyroscope sensing information (UCI HAR) and deployed on the SparkFun Edge board. This board hosts a low-power ARM Cortex-M4F-based microcontroller.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Embedded object detection applying Deep Neural Networks in railway domain 应用深度神经网络在铁路领域的嵌入式目标检测

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00093

Mikel Etxeberria-Garcia, Fernando Ezaguirre, Joanes Plazaola, Unai Muñoz, Maider Zamalloa

引用次数: 4