{"title":"System Architecture and Security Issues of Smartphone-based Point-Of-Care Devices","authors":"Christian Zajc, G. Holweg, C. Steger","doi":"10.1109/DSD51259.2020.00059","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00059","url":null,"abstract":"In recent years, personalized healthcare has become increasingly popular in our society. Wearable devices started a trend for monitoring physical health parameters. The next evolution after wearable devices are Point-Of-Care (POC) devices, which provide more vital parameter analyses for everyone. The electrification of POC devices is required to simplify the process and to increase the accuracy of measurement results. In this work, we focus on POC devices in combination with smartphones. Of Ten, these devices are measuring and processing very sensitive data, which underlie a high privacy restriction. Therefore, it is required to provide an architecture and security issue analysis of POC devices. The outcome of this research contribution provides a sensitization for the requirement of enhanced security features. Especially, to fulfill the need for a power-aware security concept for a POC system architecture, which underlies limited resources like power consumption.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130074687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Buffer Sizes Reduction for Memory-efficient CNN Inference on Mobile and Embedded Devices","authors":"S. Minakova, T. Stefanov","doi":"10.1109/DSD51259.2020.00031","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00031","url":null,"abstract":"Nowadays, convolutional neural networks (CNNs) are the core of many intelligent systems, including those that run on mobile and embedded devices. However, the execution of computationally demanding and memory-hungry CNNs on resource-limited mobile and embedded devices is quite challenging. One of the main problems, when running CNNs on such devices, is the limited amount of memory available. Thus, reduction of the CNN memory footprint is crucial for the CNN inference on mobile and embedded devices. The CNN memory footprint is determined by the amount of memory required to store CNN parameters (weights and biases) and intermediate data, exchanged between CNN operators. The most common approaches, utilized to reduce the CNN memory footprint, such as pruning and quantization, reduce the memory required to store the CNN parameters. However, these approaches decrease the CNN accuracy. Moreover, with the increasing depth of the state-of-the-art CNNs, the intermediate data exchanged between CNN operators takes even more space than the CNN parameters. Therefore, in this paper, we propose a novel approach, which allows to reduce the memory, required to store intermediate data, exchanged between CNN operators. Unlike pruning and quantization approaches, our proposed approach preserves the CNN accuracy and reduces the CNN memory footprint at the cost of decreasing the CNN throughput. Rus, our approach is orthogonal to the pruning and quantization approaches, and can be combined with these approaches for further CNN memory footprint reduction.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126380193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Amrani, Hakim Arezki, David Lellouche, Vivien Gazeau, Corinne Fillol, Oussama Allali, T. Lacroix
{"title":"Architecture of a Public Transport Supervision System Using Hybridization Models Based on Real and Predictive Data","authors":"A. Amrani, Hakim Arezki, David Lellouche, Vivien Gazeau, Corinne Fillol, Oussama Allali, T. Lacroix","doi":"10.1109/DSD51259.2020.00076","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00076","url":null,"abstract":"Management of a multimodal transport network is a challenging task and operators regularly have to deal with different types of disturbances that affect the quality of service of the transport system. To support them in their decision-making, we present the architecture of a multimodal supervision system that implements monitoring, prediction of affluence, disturbances, impacts and evaluation of functionalities focusing on one or multiples lines of the network. Our system uses the real-time data of transport operators to compute several key performance indicators (KPI) in order to monitor the network status and to detect disturbances. The prediction function is used to predict passengers’ attendance at stations, incident duration and the evolution of the whole network, in particular, phenomena emerging from the interconnections linked to the affected line. Finally, we present a use case of the supervision system applied to a real-time control of a bus line belonging to a very dense and busy segment of the multimodal transport network in Ile-de-France area.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MULTI-modal Imaging of FOREnsic SciEnce Evidence: MULTI-FORESEE Project","authors":"N. Sklavos, S. Francese","doi":"10.1109/DSD51259.2020.00068","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00068","url":null,"abstract":"In Digital Forensics science, face detection and recognition techniques are nowadays tightly connected. Investigators need accurate results delivered quickly for their official reports, in order to solve a case. Hardware implementation of face detection and recognition systems have shown to be very efficient with high recognition rate and short processing time. FPGAs are used for such implementations, because of the parallelism and the speed they can offer. In this work, we present the overview and the objectives of the MULTI-FORESEE COST project in this area. We also present alternative face detection FPGA implementations, and present face recognition techniques, for hardware integration. Finally, we compare these implementations with respect to the FPGA resources which are currently used. Efficient and flexible solutions are proposed in relation to computing power, performance, and allocated resources.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125088216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Crippa, G. Massari, F. Reghenzani, M. Zanella, W. Fornaciari
{"title":"Predictive Resource Management in Energy-constrained Embedded Systems","authors":"S. Crippa, G. Massari, F. Reghenzani, M. Zanella, W. Fornaciari","doi":"10.1109/DSD51259.2020.00035","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00035","url":null,"abstract":"The current trends in Internet of Things (IoT) lead to the deployment of low-power devices covering a wide range of application scenarios. These devices have the goal of executing simple tasks, automatically, usually with strict requirements in terms of space and cost. Typically, these devices have to rely on batteries or by harvesting energy devices (e.g., solar panels), in order to operate. On the other hand, IoT devices may be equipped with powerful multi-core CPUs to achieve performance goals, making the management of the energy budget a challenging task. This requires the development of an effective management system, that takes into account current and future energy budget availability, to dynamically bound the actual allocation of processing resources. Specifically, when exploiting solar panels for power supply, we can leverage on the weather forecast, to estimate the availability of energy in the near future. This paper introduces a predictive energy budget management system, targeting multi-core based embedded platforms. Thanks to both local and large-scale weather information, our solution aims at predicting the future incoming power and, accordingly, tuning the exploitable performance level to keep the system running under any environmental condition.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127558330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rozaliya Amirova, Vladimir Ivanov, Sergey Masyagin, Aldo Spallone, G. Succi
{"title":"Preliminary findings on tools for the analysis of mental activity of programmers using EEG data from portable devices","authors":"Rozaliya Amirova, Vladimir Ivanov, Sergey Masyagin, Aldo Spallone, G. Succi","doi":"10.1109/DSD51259.2020.00072","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00072","url":null,"abstract":"Developers are indeed the most important resource in software production, and the individual developers are hard to substitute. The core of the work of the developers of knowledge intensive systems is in their mind, and this now a growing interest in understanding how to detect and model the state of their mind. Such analysis would enable to determine and model the optimal situation to develop in terms, for instance, of speed of development, minimization of errors, etc., and, to the extent possible, to recreate or to get close to such situation while organizing the work, the processes, the tools, and so on. The problem of performing such analysis is that the most refined equipment to model the work of the mind, like the fMRI, is very expensive and not movable. However, a tool, MNE, has been developed who is able to recreate accurate approximations using EEG of the data coming from an accurate wearable device that would come from the fMRI. This is a major enabler of the research in this area and in this paper details on why to select it and how to use it are provided. Current paper makes proof-of-concept to show that EEG is applicable for for retrieving information about functional state of the brain especially with a help of MNE tool.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114306859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Amiet, Lukas Leuenberger, A. Curiger, P. Zbinden
{"title":"FPGA-based SPHINCS+ Implementations: Mind the Glitch","authors":"D. Amiet, Lukas Leuenberger, A. Curiger, P. Zbinden","doi":"10.1109/DSD51259.2020.00046","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00046","url":null,"abstract":"The digital signature scheme SPHINCS+ is a candidate in the NIST post-quantum project, whose aim is to standardize cryptographic systems that are secure against attacks originating from both quantum and classical computers. We present an efficient and, to our knowledge, first hardware implementation for SPHINCS+. Our systematic approach of a performance-optimized FPGA architecture results in a 100x speed-up compared to the reference software-only implementation. Our investigation on a real-world implementation revealed a weakness regarding fault injection. The attack breaks the scheme completely. Collecting enough private information to forge a signature is a matter of seconds on our setup. We discuss possible countermeasures. A “sign-then-verify” operation unfortunately does not detect a faulty signature, but a full replication of the hardware might make a detection possible.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimizing Picnic for Limited Memory Resources","authors":"Johannes Winkler, Andrea Höller, C. Steger","doi":"10.1109/DSD51259.2020.00041","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00041","url":null,"abstract":"Picnic is a post-quantum digital signature scheme, where the security is based on the difficulty of inverting a symmetric block cipher and zero-knowledge proofs. However, generating a Picnic signature to a specific message requires up to 300 kB content depending RAM. As the memory of an IoT device is limited this can lead to issues at the implementation. Our target is bringing post-quantum cryptography to IoT systems. We propose three structural adjustments of the Picnic algorithm to reduce the memory usage. Two adjustments are compatible with the reference implementation, one of them breaks backward compatibility. We show analytically that the content depending memory for generating a signature can be decreased to under 10 kB.With these adjustments, Picnic becomes suitable for IoT devices with little RAM. Since our approach also aims at easier parallelization, a speed-up depending on the number of instances is possible.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115932480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs","authors":"Lukás Kekely, Jakub Cabal, V. Pus, J. Korenek","doi":"10.1109/DSD51259.2020.00020","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00020","url":null,"abstract":"As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses. The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400Gbps, lTbps and even 2 Tbps Ethernet links.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122688282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DSD 2020 Index","authors":"","doi":"10.1109/dsd51259.2020.00112","DOIUrl":"https://doi.org/10.1109/dsd51259.2020.00112","url":null,"abstract":"","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122838176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}