2020 23rd Euromicro Conference on Digital System Design (DSD)最新文献_第2页

Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers 面向数据中心联网加速器集成的硬件和软件组件

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00033

Fritjof Steinert, Niklas Schelten, Anton Schulte, B. Stabernack

引用次数: 6

Active Redundant Hardware Architecture for Increased Reliability in FPGA-Based Nuclear Reactors Critical Systems 基于fpga的核反应堆关键系统中提高可靠性的主动冗余硬件架构

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00100

M. Farias, N. Nedjah, P. V. Carvalho

{"title":"Active Redundant Hardware Architecture for Increased Reliability in FPGA-Based Nuclear Reactors Critical Systems","authors":"M. Farias, N. Nedjah, P. V. Carvalho","doi":"10.1109/DSD51259.2020.00100","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00100","url":null,"abstract":"The hunt for increased reliability in systems for critical applications is a never-ending process and is a point of concern for designers in several different fields, such as nuclear reactors. This concern becomes more prominent when a new device technology is integrated into the options for the development of those systems, such as programmable logic devices like the FPGA. With the constant breakthroughs in this technology, there has been an increase in the capacity and the performance of FPGAs. Nevertheless, new methods to keep fault tolerance at an appropriate level for critical applications in hardware must be considered, particularly due to the transient nature of some radiation-induced faults. This work proposes a resilient and adaptable hardware architecture that increases the reliability of circuits implemented in FPGAs, based on a classic active redundancy model, Triple Modular Redundancy with spares. Also, it brings forth a novel hardware architecture that can easily be ported to different FPGA models without compromising performance, reliability, and availability. We discuss and analyze these requirements for the proposed architecture and show that it is more reliable and keeps this reliability for longer periods of time than redundant solutions that use more area.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126565534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems 高性能安全关键系统的自我监控可靠平台

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00066

Carles Hernández, Jose Flieh, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, J. Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, J. Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, F. Rammerstorfer, C. Schwarzl, Franck Wartet, Dierk Lüdemann, M. Labayen

{"title":"SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems","authors":"Carles Hernández, Jose Flieh, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, J. Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, J. Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, F. Rammerstorfer, C. Schwarzl, Franck Wartet, Dierk Lüdemann, M. Labayen","doi":"10.1109/DSD51259.2020.00066","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00066","url":null,"abstract":"Existing HW/SW platforms for safety-critical systems suffer from limited performance and/or from lack of flexibility due to building on specific proprietary components. This jeopardizes their wide deployment across domains. While some research has been done to overcome these limitations, they have had limited success owing to missing flexibility and extensibility. Flexibility and extensibility are the cornerstones of industry adoption: industries dealing in capital goods need technologies on which they can rely on during decades (e.g. avionics, space, automotive). SELENE aims at covering this gap by proposing a new family of safety-critical computing platforms, which builds upon open source components such as the RISC-V instruction set architecture, GNU/Linux, and the Jailhouse hypervisor. SELENE will develop an advanced computing platform that is able to: (1) adapt the system to the specific requirements of different application domains, to changing environmental conditions, and to internal conditions of the system itself; (2) allow the integration of applications of different criticalities and performance demands in the same platform, guaranteeing functional and temporal isolation properties; (3) achieve flexible diverse redundancy by exploiting the inherent redundant capabilities of the multicore; and (4) efficiently execute compute-intensive applications by means of specific accelerators.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"24 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults 智能电子锁软件对随机和故意故障的强化

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00110

Jakub Lojda, R. Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Z. Kotásek

{"title":"Hardening of Smart Electronic Lock Software against Random and Deliberate Faults","authors":"Jakub Lojda, R. Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Z. Kotásek","doi":"10.1109/DSD51259.2020.00110","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00110","url":null,"abstract":"In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Programmable SoC Implementation of the DGK Cryptosystem for Privacy-Enhancing Technologies 用于隐私增强技术的DGK密码系统的可编程SoC实现

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00049

Milad Bahadori, K. Järvinen

引用次数: 0

Challenges of Return-Oriented-Programming on the Xtensa Hardware Architecture 面向返回的编程在Xtensa硬件架构中的挑战

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00034

Kai Lehniger, Marcin Aftowicz, P. Langendörfer, Z. Dyka

引用次数: 6

Design of Compact Integrated Photonic Crystal NAND and NOR Logic Gates 紧凑集成光子晶体NAND和NOR逻辑门的设计

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00073

L. P. Caballero, M. Povinelli, J. Ramirez, P. Guimarães, O. V. Neto

{"title":"Design of Compact Integrated Photonic Crystal NAND and NOR Logic Gates","authors":"L. P. Caballero, M. Povinelli, J. Ramirez, P. Guimarães, O. V. Neto","doi":"10.1109/DSD51259.2020.00073","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00073","url":null,"abstract":"Here we propose an integrated and compact photonic crystal (PhC) device that can operate as a NAND or NOR logic gate. It is designed in a PhC slab composed of GaAs/AlGaAs heterostructure and a 2D pattern of a triangular lattice of holes. By modifying target holes on the structure, the NAND or NOR gates are achieved. They are universal logic functions, which means that any logic function can be accomplished by connecting them. We perform simulations through the FDTD method to prove the correct operation of our integrated and compact device. The simulation results show that the upper power limit to represent the logic 0 is $0.17P_{in}$, where Pin is the input power. On the other hand, the lower power limit to represent the logic 1 is found to be $0.50P_{in}$. The NAND and NOR logic gates implemented here present a response time of 5 ps, resulting in a clock rate of 200 GHz. They also operate within the C band of the telecommunication window. Finally, we highlight that our integrated and compact PhC device has great potential to be microfabricated as it is based on a practical and efficient approach for fabrication. It also can be incorporated easily on integrated photonics technology.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131189800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

The VALU3S ECSEL Project: Verification and Validation of Automated Systems Safety and Security VALU3S ECSEL项目:自动化系统安全和安保的验证和确认

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00064

R. Barbosa, Stylianos Basagiannis, G. Giantamidis, H. Becker, E. Ferrari, J. Jahic, A. Kanak, M. L. Esnaola, V. Orani, D. Pereira, L. Pomante, R. Schlick, A. Smrčka, A. Yazıcı, P. Folkesson, B. Sangchoolie

{"title":"The VALU3S ECSEL Project: Verification and Validation of Automated Systems Safety and Security","authors":"R. Barbosa, Stylianos Basagiannis, G. Giantamidis, H. Becker, E. Ferrari, J. Jahic, A. Kanak, M. L. Esnaola, V. Orani, D. Pereira, L. Pomante, R. Schlick, A. Smrčka, A. Yazıcı, P. Folkesson, B. Sangchoolie","doi":"10.1109/DSD51259.2020.00064","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00064","url":null,"abstract":"Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present an ECSEL JU project (VALU3S) that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133115158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials 结合机器学习和小数据应用的形式化技术——探索新结构材料的框架

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00087

R. Drechsler, S. Huhn, Christina Plump

{"title":"Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials","authors":"R. Drechsler, S. Huhn, Christina Plump","doi":"10.1109/DSD51259.2020.00087","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00087","url":null,"abstract":"The massive increase in computation power leads to a renaissance of supervised learning techniques, which were published decades ago but have so far been confined to theory. These techniques form the increasingly important field of Machine Learning (ML), which contributes to a large variety of research concerning industrial, automotive but also consumer applications strongly influencing our daily life. Commonly, the learning techniques require a set of labeled data, which involves a resource-intensive generation, to conduct the training. Depending on the dimensionality of the data and the required precision as needed by the application, the amount of training data varies. In case of insufficient training data, the prediction is of low-quality or not even possible at all, restricting the applicability of ML. This work proposes a combination of formal techniques and ML to implement a framework that allows coping with high-dimensional, training data while retaining a high prediction quality. The efficacy of this method is exemplarily demonstrated on the basis of an interdisciplinary material science research problem concerning the development of new structural materials, though it can be adapted to further applications.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks 用于减轻缓存逻辑侧通道攻击的安全缓存备选地址表

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00043

Ameer Shalabi, Tara Ghasempouri, P. Ellervee, J. Raik

引用次数: 2