Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip

In this paper, a novel, highly configurable framework for low power and error-resilient System-On-Chip is presented. The framework is composed, on the one hand, of the SWIELD configurable flip-flop and on the other hand, of the Chameleon controller. The SWIELD flip-flop is able to operate in three modes. It is driven/configured during runtime via the dedicated controller called Chameleon System Operation Management Unit. The proposed framework is integrated into a complex SoC based on a 32-bit general-purpose processor and the entire system is synthesized using the IHP $130 nm$ technology library. Numerous simulation experiments have been conducted in order to estimate the system error resilience and power consumption. At expense of negligible area and complexity overhead, the introduced framework shows great potential and excellent results w.r.t. both metrics of interest.