2020 23rd Euromicro Conference on Digital System Design (DSD)最新文献_第7页

Non-Homogeneous Continuous Time Markov Chains Calculations 非齐次连续时间马尔可夫链计算

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00108

J. Reznícek, Martin Kohlík, H. Kubátová

引用次数: 3

Comparison of three counter value based ROPUFs on FPGA 基于FPGA的三种计数器值的ropuf的比较

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00042

Filip Kodýtek, R. Lórencz, J. Bucek

引用次数: 1

Novel Controller for Dummy Rounds Scheme DPA Countermeasure 一种新型假弹控制器方案DPA对抗

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00053

Petr Moucha, Stanislav Jerabek, M. Novotný

引用次数: 0

Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops 三模冗余TSPC人字拖辐射硬化设计概念

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00101

O. Schrape, M. Andjelković, A. Breitenreiter, A. Balashov, M. Krstic

{"title":"Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops","authors":"O. Schrape, M. Andjelković, A. Breitenreiter, A. Balashov, M. Krstic","doi":"10.1109/DSD51259.2020.00101","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00101","url":null,"abstract":"A robust design, which is one of the main requirements for space applications is always a tradeoff between power and area budget, speed requirement and the overall reliability. The occurrence of Single Event Effects (SEE) induced by energetic particle hits in the silicon leads to the insertion of additional replica logic at the design phase in order to tolerate Single Event Upsets (SEU) or Single Event Transients (SET). One of the most traditional circuit design technique is Triple Modular Redundancy (TMR). This paper presents a design concept for Radiation-Hardness-by-Design (RHBD) of TMR standard cell gates with local SET filter on the datapath, composed of True Single-Phase Clock (TSPC) flip-flops. The circuit architecture of the novel TSPC$- Delta$ TMR flip-flops is discussed and compared to the baseline standard cell D-flip-flop. Analog simulations under various process, voltage, and temperature (PVT) conditions show an improvement by 50% of the gate delay of the baseline TSPC flip-flop. Moreover, the proposed TSPC$- Delta$ TMR gate candidate has a delay overhead of only 130ps under worst case condition compared to the classical unhardened D-latch-based reference flip-flop. Test vehicles for electrical measurements and radiation tests are implemented in $0.13 mu mathrm{m}$ BiCMOS technology.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124491858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Adaptive MEMS Mirror Control for Reliable Automotive Driving Assistance Applications 可靠的汽车驾驶辅助应用的自适应MEMS后视镜控制

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00080

I. Maksymova, P. Greiner, C. Steger, L. Niedermueller, N. Druml

引用次数: 3

Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays 阵列形状和内存带宽对CNN收缩阵列执行时间的影响

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00086

Eduardo Yago, Pau Castelló, S. Petit, M. E. Gómez, J. Sahuquillo

{"title":"Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays","authors":"Eduardo Yago, Pau Castelló, S. Petit, M. E. Gómez, J. Sahuquillo","doi":"10.1109/DSD51259.2020.00086","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00086","url":null,"abstract":"The use of Convolutional Neural Networks (CNN) has experienced a huge rise over the last recent years and its popularity has increased exponentially, mainly due to its application both for image recognition and certain applications related to artificial intelligence. The new applications of CNN request computing demands that are difficult to address by conventional processors.As a consequence, accelerators –both prototypes and commercial products– focusing on CNN computation have been proposed. Among these accelerators, those based on systolic arrays have acquired a special relevance; some examples are the Google’s TPU and Eyeriss.Current research has focused on regular squared systolic arrays and most existing work assumes that there is enough memory bandwidth to feed the systolic array with input data. In this paper we explore the design of non-squared systolic arrays and address the impact of the memory bandwidth from a performance perspective.This work makes two main contributions. First, we found that some workloads with non-squared arrays achieve similar performance to systolic arrays twice as large, which can translate in area and/or energy benefits.Second, we present a performance comparison varying the main memory bandwidth for current DRAM devices. The analysis reveals that main memory bandwidth has a great impact on performance and that the decision of which technology use is key for the system performance. For the 64x64 array size it is necessary to use HBM2 memory to avoid the slowdown that would introduce cheaper technologies (e.g. DDR5 and DDR4).","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Lightweight Security Data Streaming, Based on Reconfigurable Logic, for FPGA Platform 基于可重构逻辑的FPGA平台轻量级安全数据流

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00052

Marios Tsavos, N. Sklavos, G. Alexiou

{"title":"Lightweight Security Data Streaming, Based on Reconfigurable Logic, for FPGA Platform","authors":"Marios Tsavos, N. Sklavos, G. Alexiou","doi":"10.1109/DSD51259.2020.00052","DOIUrl":"https://doi.org/10.1109/DSD51259.2020.00052","url":null,"abstract":"Alongside the rapid expansion of Internet of Things (IoT), and network evolution (5G, 6G technologies), comes the need for security of higher level and less hardware demanding modules. New cryptographic systems are developed, in order to satisfy the special needs of security, that have emerged in modern applications. In this paper, a novel lightweight data streaming system, is proposed, which operates in alternative modes. Each one of them, performs efficiently as one of three in total, stream ciphering modules. The operation of the proposed system, is based on reconfigurable logic. It aims at a lower hardware utilization and good performance, at the same time. In addition, in order to have a fair and detailed comparison, a second one design is also integrated and introduced. This one proposes a conventional architecture, consisting of the same three stream ciphering modes, implemented on the same device, as separate operation modules. The FPGA synthesis results prove that the proposed reconfigurable design achieves to minimize the area resources, from 18% to 30%, compared to the conventional one, while maintaining high performance values, for the supported modes.","PeriodicalId":128527,"journal":{"name":"2020 23rd Euromicro Conference on Digital System Design (DSD)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128168408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Key Enabling Technologies for Drones 无人机关键使能技术

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00083

Mahmoud Hussein, R. Nouacer, Yassine Ouhammou, E. Villar, Federico Corradi, Carlo Tieri, Rodrigo Castiñeira

引用次数: 7

PET-to-MLIR: A polyhedral front-end for MLIR PET-to-MLIR:用于MLIR的多面体前端

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00091

Konrad Komisarczyk, Lorenzo Chelini, K. Vadivel, Roel Jordans, H. Corporaal

引用次数: 4

The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform ECSEL分形项目:基于独特的开放、安全、可靠、低功耗硬件平台的认知分形和安全边缘

2020 23rd Euromicro Conference on Digital System Design (DSD) Pub Date : 2020-08-01 DOI: 10.1109/DSD51259.2020.00069

A. Lojo, Leire Rubio, J. Ruano, T. D. Mascio, L. Pomante, E. Ferrari, I. G. Vega, Frank K. Gürkaynak, M. L. Esnaola, V. Orani, J. Abella

引用次数: 5