Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops

Abstract

A robust design, which is one of the main requirements for space applications is always a tradeoff between power and area budget, speed requirement and the overall reliability. The occurrence of Single Event Effects (SEE) induced by energetic particle hits in the silicon leads to the insertion of additional replica logic at the design phase in order to tolerate Single Event Upsets (SEU) or Single Event Transients (SET). One of the most traditional circuit design technique is Triple Modular Redundancy (TMR). This paper presents a design concept for Radiation-Hardness-by-Design (RHBD) of TMR standard cell gates with local SET filter on the datapath, composed of True Single-Phase Clock (TSPC) flip-flops. The circuit architecture of the novel TSPC$- \Delta$ TMR flip-flops is discussed and compared to the baseline standard cell D-flip-flop. Analog simulations under various process, voltage, and temperature (PVT) conditions show an improvement by 50% of the gate delay of the baseline TSPC flip-flop. Moreover, the proposed TSPC$- \Delta$ TMR gate candidate has a delay overhead of only 130ps under worst case condition compared to the classical unhardened D-latch-based reference flip-flop. Test vehicles for electrical measurements and radiation tests are implemented in $0.13 \mu \mathrm{m}$ BiCMOS technology.