Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation

Abstract

A number of works have focused on relaxing circuit specification for building partial TMR circuits, but a framework for analysing the effect of circuit degradation on its dependability is missing in the literature. This paper aims to bridge this gap by developing a reliability model for approximate TMR circuits implemented in FPGAs and the parameter definitions for controlling design trade-offs with reliability in the approximation process. The framework is useful in the assignment of the design parameters such that the reliability constraints of the application at hand are satisfied. Reliability curves for different trade-offs show a sharp decline in reliability even at small error thresholds, requiring that for maintaining system operation in the high reliability region, a TMR approximation method must achieve the desired reduction in hardware overheads within tight error constraints. Furthermore, the effect of an unprotected voter on the overall system reliability is also quantified. To which end, it is shown that the simple unprotected voter results in significant degradation on the approximate TMR reliability and therefore using a fault-tolerant voting circuit is essential to a reliable system operation.