20th International Symposium on Quality Electronic Design (ISQED)最新文献

{"title":"Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation","authors":"Xiaobang Liu, R. Vemuri","doi":"10.1109/ISQED.2019.8697793","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697793","url":null,"abstract":"Limited observability and controllability are the major challenges in post-silicon validation and debugging. Therefore trace buffer based run-time techniques have been proposed and applied to post-silicon validation for bug detection and localization. Assertions are widely used in pre-silicon verification to monitor if certain functional scenarios are working properly. In post-silicon validation, assertion checkers can be synthesized into the original design for enhanced visibility and debugging. However, hardware assertion checkers introduce additional area overhead. In this paper, we propose a method for trace signal selection for maximizing assertion coverage using SAT-based signal restoration algorithm without introducing any additional hardware. Experimental results show that the proposed methods can significantly improve the assertion coverage (up to 187.5%) compared to the use of forward propagation and backward justification (FB) based signal restoration algorithm for trace signal selection.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Welcome to ISQED 2019","authors":"","doi":"10.1109/isqed.2019.8697777","DOIUrl":"https://doi.org/10.1109/isqed.2019.8697777","url":null,"abstract":"","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors","authors":"Jawad Haj-Yahya, Efraim Rotem, A. Mendelson, A. Chattopadhyay","doi":"10.1109/ISQED.2019.8697544","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697544","url":null,"abstract":"The continuous quest for energy-efficient computing has led towards the adoption of fine-grained controls in processor sub-systems, of which power delivery network is the most prominent one. Recent industry trends reflect a shift towards on-chip, integrated voltage regulator (IVRs) to that effect. We undertake a thorough and quantitative evaluation of different power delivery networks for modern microprocessors. In contrast to the current trend, we conclude that IVR schemes perform worse compared to the conventional off-chip voltage regulator scheme. Further, we present studies on diverse workloads and Thermal Design Points (TDPs) to highlight the importance of workload-specific power delivery scheme. To the best of our knowledge, this is the first comprehensive study across processors' TDPs and workloads.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copyright","authors":"","doi":"10.1109/isqed.2019.8697872","DOIUrl":"https://doi.org/10.1109/isqed.2019.8697872","url":null,"abstract":"","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126677802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience","authors":"A. Roohi, Shaahin Angizi, Deliang Fan, R. Demara","doi":"10.1109/ISQED.2019.8697572","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697572","url":null,"abstract":"Herein, a bit-wise Convolutional Neural Network (CNN) in-memory accelerator is implemented using Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) computational sub-arrays. It utilizes a novel AND-Accumulation method capable of significantly-reduced energy consumption within convolutional layers and performs various low bitwidth CNN inference operations entirely within MRAM. Power-intermittence resiliency is also enhanced by retaining the partial state information needed to maintain computational forward-progress, which is advantageous for battery-less IoT nodes. Simulation results indicate $sim pmb{5.4}timesmathbf{ higher}$ energy-efficiency and $9timesmathbf{speedup}$ over ReRAM-based acceleration, or roughly $sim pmb{9.7}times mathbf{higher}$ energy-efficiency and $pmb{13.5}timesmathbf{speedup}$ over recent CMOS-only approaches, while maintaining inference accuracy comparable to baseline designs.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130661389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug","authors":"Yuting Cao, Hao Zheng, S. Ray","doi":"10.1109/ISQED.2019.8697394","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697394","url":null,"abstract":"Reconstruction of how components communicate with each other during system execution is crucial for debugging system-on-chip designs. However, limited observability is the major obstacle to the efficient and accurate reconstruction in the post-silicon validation stage. This paper addresses that problem by proposing several communication event selection methods guided by system-level communication protocols. Such methods are optimized for on-chip communication event tracing infrastructure to enhance observability. The effectiveness of these methods are demonstrated with experiments on a non-trivial multicore SoC prototype. The results show that with the proposed method, more comprehensive information on system internal execution can be inferred from traces under limited observability.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"730 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ISQED 2019 Best Paper","authors":"Masoud Zabihi, Zhengyang Zhao, D. Mahendra, Z. Chowdhury, Salonik Resch, Thomas J. Peterson, Ulya R. Karpuzcu, Jianping Wang, S. Sapatnekar","doi":"10.1109/isqed.2019.8697521","DOIUrl":"https://doi.org/10.1109/isqed.2019.8697521","url":null,"abstract":"Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform Masoud Zabihi1 , Zhengyang Zhao1 , Mahendra DC2 , Zamshed I. Chowdhury1 Salonik Resch1 , Thomas Peterson2 , Ulya R. Karpuzcu1 , Jian-Ping Wang1 Sachin S. Sapatnekar1 1Department of Electrical and Computer Engineering, University of Minnesota 2School of Physics and Astronomy, University of Minnesota ISQED 2019 Best Paper","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115058889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ISQED 2019 Organizing Committee","authors":"Deliang Fan","doi":"10.1109/isqed.2019.8697570","DOIUrl":"https://doi.org/10.1109/isqed.2019.8697570","url":null,"abstract":"Japan Chair Masahiro Fujita University of Tokyo Taiwan Chair Shih-Hsu Huang Chung Yuan Christian University Brazil & South America Chair Fabiano Passuelo Hessel Pontificia Universidade Catolica do Rio do Sul, Brazil Europe Chair George P. Alexiou University of Patras and RA-CTI, Patras, Greece Panel Chair Tuna Tarim Texas Instruments Organizing Committe Chair Steve Heinrich-Barna Texas Instruments","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131134022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards Energy Efficient non-von Neumann Architectures for Deep Learning","authors":"Antara Ganguly, R. Muralidhar, Virendra Singh","doi":"10.1109/ISQED.2019.8697354","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697354","url":null,"abstract":"Deep learning algorithms have taken learning-based applications by storm because of their algorithmic accuracy in modeling complex patterns, classification tasks and prediction problems across a wide range of applications like image processing, autonomous driving, pattern recognition, etc. This has come about due to several factors - improved computation capabilities with GPUs, improved memory technologies (near-data processing, High Bandwidth Memory, Hybrid Memory Cube and non-volatile memory) that have enabled us to break the memory wall), dedicated accelerators, FPGA implementations and so on. Since these workloads primarily constitute shuttling large datasets between the main memory and the processing station(s), several non-von Neumann approaches have also been implemented through dataflow computing, neuromorphic chips, Spiking neural network-based machines, and other brain-inspired computing technologies. While these technological advances have improved the accuracy of deep learning algorithms and made neuromorphic and non-von Neumann implementations possible, substantial challenges remain ahead. From a systems perspective, it is not clear how overall system level energy efficiency can be modeled, estimated and coordinated across such diverse computing architectures. Furthermore, a large class of deep learning algorithms that benefit from these advances run predominantly on “edge” devices such as in autonomous cars, and hence, overall power consumption and energy efficiency are of the highest importance. This paper makes the following contributions - we present an architectural analysis of deep learning and how they have benefited from modeling its algorithms as dataflows and representing the dataflows as “neurons”, and when modeled as non-von Neumann architectures, have drastically improved the performance and accuracy of these workloads. We then present a landscape of different CNN implementations across von Neumann and non-von Neumann models. Subsequently, we look at system level energy efficiency considerations (energy models, abstractions, estimation methodologies, standards and benchmarks) for deep learning systems built with such diverse architectures and technologies and discuss some open problems, challenges and opportunities for both industry and research communities.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131563571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment","authors":"Xiaokun Yang, Yunxiang Zhang, Lei Wu","doi":"10.1109/ISQED.2019.8697816","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697816","url":null,"abstract":"This paper presents a scalable image/video processing platform on Field-Programmable Gate Array (FPGA), capable of capturing images via a low-cost OV7670 camera and in real time displaying the original, in-process, and final results of images on a VGA-interfaced monitor. To make the platform expandable and reusable, not only is the design with Verilog hardware description language (HDL) offered, but also the verification environment including six open verification components (OVCs) is provided. To the best of our knowledge, this proposed work costs the least FPGA resource (753 LUTs and 277 Register) compared to the existing open source implementations on the design of the Camera-FPGA-VGA data path. We make this platform publicly available to encourage future research projects on image/video processing, computer vision, machine learning, etc., and to serve educational studies on digital system design with Verilog HDL and FPGAs.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134564684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}