20th International Symposium on Quality Electronic Design (ISQED)最新文献_第5页

A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking 基于状态编码的有限状态机水印的达尔文遗传算法

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697760

Matthew Lewandowski, S. Katkoori

引用次数: 0

Closing the Verification Gap with Static Sign-off 通过静态签名关闭验证缺口

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697608

P. Ashar, V. Viswanath

{"title":"Closing the Verification Gap with Static Sign-off","authors":"P. Ashar, V. Viswanath","doi":"10.1109/ISQED.2019.8697608","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697608","url":null,"abstract":"It is commonly held that because SOCs are extremely complex, the gap between the ability to design and to verify is beyond manageable proportions. Recent reality, though, has been more positive. The recent increase in SOC scale has been enabled by design-style advances, and the increase in SOC scale has been much more rapid than that of constituent IP. Consequently, verification complexity and SOC failure is now more correlated to SOC implementation schemes than IP functionality. In this milieu, SOC sign-off appears more manageable when broken into verification problems posed by the individual SOC implementation schemes, each scheme characterized by a narrow range of failure risks that can be modeled precisely. This tends to be a sweet spot for “static analysis”, which is a general term for methods that are based on algorithmically analyzing design attributes rather than testing a design by evaluating input stimuli through them. In fact, the dissection of SOC verification into the individual verification problems and the development of failure-specific static analysis methods for them has been the verification revolution of the past decade, without which the SOC revolution would have stalled.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks 基于神经网络的预强调可调I/O驱动行为建模

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697597

Huan Yu, J. Shin, T. Michalka, M. Larbi, M. Swaminathan

引用次数: 3

Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function 概率自旋逻辑在布尔函数可满足性检测中的应用

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697357

Vaibhav Agarwal, Sneh Saurabh

{"title":"Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function","authors":"Vaibhav Agarwal, Sneh Saurabh","doi":"10.1109/ISQED.2019.8697357","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697357","url":null,"abstract":"Probabilistic Spin Logic (PSL) is a computing model that can be implemented using stochastic units (called p-bits) such as low-barrier nanomagnets. Besides computing a given Boolean function, PSL can also compute the inverse of the function. In this paper, we propose a methodology to exploit the invertibility of PSL in detecting the satisfiability (SAT) of a given Boolean function. First, we propose an algorithm to derive a PSL implementation for any Boolean function given in Conjunctive Normal Form (CNF). For a given SAT problem in CNF, we realize the given function in PSL using the proposed algorithm, clamp only the output to logic ‘1’ and detect the satisfiability of the given function by observing the probability distribution of the possible states. We demonstrate that PSL is highly selective of the satisfiable input patterns even for tough problems where only one out of one million input patterns is satisfiable. A key parameter deciding the effectiveness of the proposed technique is the time that is allowed for PSL computation, which would ultimately depend on the characteristics of the PSL hardware implementation.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Automated Design Flow for Synthesis of Optimal Switching Power Supply 综合最优开关电源的自动化设计流程

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697699

P. Chawda, A. Prasad, K. Rathod, Kritika Solanki

引用次数: 0

Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms 利用优化算法提高数字电路性能的稳健性晶体管尺寸

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697718

Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas

引用次数: 7

Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application 用于高速非易失性SRAM的低恢复能量差自旋霍尔效应MRAM

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697426

S. Shreya, B. Kaushik

引用次数: 3

Proceedings - ISQED 2019

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/isqed.2019.8697719

引用次数: 0

Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices 可穿戴设备二值化神经网络推理的分类能量最小化

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697574

M. Hosseini, Hirenkumar Paneliya, Utteja Kallakuri, Mohit Khatwani, T. Mohsenin

{"title":"Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices","authors":"M. Hosseini, Hirenkumar Paneliya, Utteja Kallakuri, Mohit Khatwani, T. Mohsenin","doi":"10.1109/ISQED.2019.8697574","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697574","url":null,"abstract":"In this paper, we propose a low-power hardware for efficient deployment of binarized neural networks (BNNs) that have been trained for physiological datasets. BNNs constrain weights and feature-map to 1 bit, can pack in as many 1-bit weights as the width of a memory entry provides, and can execute multiple multiply-accumulate (MAC) operations with one fused bit-wise xnor and population-count instruction over aligned packed entries. Our proposed hardware is scalable with the number of processing engines (PEs) and the memory width, both of which adjustable for the most energy efficient configuration given an application. We implement two real case studies including Physical Activity Monitoring and Stress Detection on our platform, and for each case study on the target platform, we seek the optimal PE and memory configurations. Our implementation results indicate that a configuration with a good choice of memory width and number of PEs can be optimized up to 4x and 2.5 x in energy consumption respectively on Artix-7 FPGA and on 65nm CMOS ASIC implementation. We also show that, generally, wider memories make more efficient BNN processing hardware. To further reduce the energy, we introduce Pool-Skipping technique that can skip at least 50% of the operations that are accompanied by a Max-Pool layer in BNNs, leading to 37% operation reduction in the Stress Detection case study. Compared to the related works using the same case studies on the same target platform and with the same classification accuracy, our hardware is respectively 4.5x and 250x more energy efficient for the Stress Detection on FPGA and Physical Activity Monitoring on ASIC, respectively.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129955829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks 用于循环神经网络的具有三维集成的特定应用处理器体系结构

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697413

Sumon Dey, P. Franzon

{"title":"An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks","authors":"Sumon Dey, P. Franzon","doi":"10.1109/ISQED.2019.8697413","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697413","url":null,"abstract":"Deep learning using recurrent neural networks has broadened the horizon of artificial intelligence. It can process a massive amount of multimodal natural data (video, audio) and learn useful join representations in various applications. However, implementation of recurrent neural networks in hardware and learn representations requires high throughput and memory bandwidth of that hardware platform. This work offers a 3D hardware architecture with application-specific instruction set processor, 3D-stacked memory, and sized on-chip memory for training and inference of recurrent neural networks. It also implemented a set of short instructions after analyzing different complex, time-consuming, special operations into high-level function blocks. The accelerator also performed state-of-the-art mixed precision training using custom instructions. A high-level programming environment is developed to generate Very Long Instruction Word (VLIW) instructions for this accelerator and processed a popular and successful variant of the recurrent neural network. At 28nm, this work achieved 8.5 x processing speedup, 47.5 x energy efficiency per sequence, and 2.71 x reduction in silicon area against a GPU.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133557769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3