20th International Symposium on Quality Electronic Design (ISQED)最新文献

{"title":"A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design","authors":"Shantonu Das, D. Kim","doi":"10.1109/ISQED.2019.8697605","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697605","url":null,"abstract":"In this paper, we propose a non-slicing 3-D floorplan representation to design block-level monolithic 3-D ICs, The new 3-D floorplan representation applied to simulated annealing-based optimization achieves smaller volume, shorter wire length, and lower dynamic power consumption than the Sequence Triple, Sequence Quintuple, and Slicing Tree 3-D floorplanning representations.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134093544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lightweight Secure-Boot Architecture for RISC-V System-on-Chip","authors":"Jawad Haj-Yahya, M. Wong, V. Pudi, S. Bhasin, A. Chattopadhyay","doi":"10.1109/ISQED.2019.8697657","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697657","url":null,"abstract":"Securing thousands of connected, resource-constrained computing devices is a major challenge nowadays. Adding to the challenge, third party service providers need regular access to the system. To ensure the integrity of the system and authenticity of the software vendor, secure boot is supported by several commercial processors. However, the existing solutions are either complex, or have been compromised by determined attackers. In this scenario, open-source secure computing architectures are poised to play an important role for designers and white hat attackers. In this manuscript, we propose a lightweight hardware-based secure boot architecture. The architecture uses efficient implementation of Elliptic Curve Digital Signature Algorithm (ECDSA), Secure Hash Algorithm 3 (SHA3) hashing algorithm and Direct Memory Access (DMA). In addition, the architecture includes Key Management Unit, which incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation. We demonstrated the framework on RISC-V based SoC. Detailed analysis of performance and security for the platform is presented.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Task-Based Neuromodulation Architecture for Lifelong Learning","authors":"A. Daram, D. Kudithipudi, A. Yanguas-Gil","doi":"10.1109/ISQED.2019.8697362","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697362","url":null,"abstract":"The conventional supervised deep learning frameworks for image classification focus on finding the minimizer of an objective function. However, for a lifelong learning system, a network has to be able to dynamically learn new tasks from very few examples. In biological neural networks, it is observed that neuromodulation acts as a key factor in continual learning. In this work, we propose a dynamic learning system, ModNet, wherein a modulatory unit regulates the learning depending on the context and the internal state of the system. The modulatory unit, which consists of a group of neurons, exercises the use of neuromodulation and Hebbian plasticity mechanisms over a population of neurons instead of relying on backpropagation of error gradients. An efficient digital architecture with on-chip training and resource sharing is proposed to facilitate the efficacy of task-based processing.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"802 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power-aware IoT based Smart Health Monitoring using Wireless Body Area Network","authors":"Jitumani Sarma, Akash Katiyar, Rakesh Biswas, H. Mondal","doi":"10.1109/ISQED.2019.8697739","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697739","url":null,"abstract":"In Internet of Things (IoT), large amount of data are processed and communicated through different wireless sensor network technologies. For smart health-care application, Wireless Body Area Network (WBAN) which is based on IoT can connect wearable devices to monitor different biomedical signals. In order to ensure continuous monitoring of health over a long period of time in WBAN, power management is a key requirement. A power management technique for prolong and continuous ECG monitoring based on critical data and energy level of battery is proposed in this paper. To reduce the power consumption, a light-weight power management controller is introduced based on the present status of ECG data and battery. The proposed architecture saves up to 27% power consumption in WBAN compared to the conventional architecture without incurring significant overhead.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115904406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET","authors":"Hung-Han Lin, V. Hu","doi":"10.1109/ISQED.2019.8697625","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697625","url":null,"abstract":"In this work, the device design and analog performance of GaAsSb/InGaAs negative-capacitance vertical-tunnel FET (NCVT-FET) are analyzed compared with TFET. The optimized device design of NCVT-FET is proposed to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. The impacts of source overlap length, tunnel layer, and $mathrm{N}++$ doping concentration have been investigated. The optimized NCVT-FET exhibits small $mathrm{I}_{mathrm{off}} (10 mathrm{pA}/mu mathrm{m})$ and large $mathrm{I}_{mathrm{on}}(405mu mathrm{A}/mu mathrm{m})$ at $mathrm{V}_{mathrm{DD}}=0.5mathrm{V}$ with 14mV/decade sub $mathrm{V}_{mathrm{t}}$ swing over 4 decades of current were obtained. Moreover, the optimized NCVT-FET shows higher transconductance $mathrm{g}_{mathrm{m},max}(+92%)$, higher $mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{DS}}$, and larger cutoff frequency $mathrm{f}_{mathrm{T},max}(+75%)$ compared to TFET.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130225957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation Based Assessment of SRAM Data Retention Voltage","authors":"Zhipeng Dong, Xingang Cao, M. A. U. Karim, V. Joshi, T. Klick, J. Schmid","doi":"10.1109/ISQED.2019.8697425","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697425","url":null,"abstract":"With the continued scaling of MOSFET feature size, reducing the SoC power consumption has become one of the main challenges for the semiconductor industry. Lowering the data retention voltage $(mathrm{V}_{mathrm{ret}})$ can significantly improve the SRAM standby power, which has become one of the dominant components of the overall system power consumption. Therefore, an accurate assessment of SRAM $mathrm{V}_{mathrm{ret}}$ is of critical importance to determine the lowest $mathrm{V}_{mathrm{ret}}$ specification for the SRAM array that still meets the overall product yield target. In this work, the data retention voltage distribution of a 22nm 6T SRAM array is studied through variation aware transient SPICE simulation and compared to Si data. The results show that parametric device variability based intrinsic simulation is insufficient to estimate the data retention voltage of SRAM array. The effect of gate oxide short (GOS), an extrinsic gate leakage mechanism, on the $mathrm{V}_{mathrm{ret}}$ distribution of SRAM array is studied, and it indicates that data retention voltage is especially sensitive to gate oxide shorts. It is shown that gate-drain oxide short and pull-down (PD) transistor gate-source oxide short are the most probable extrinsic mechanisms limiting the yield of the 22nm SRAM array. By accounting both intrinsic and extrinsic effects, an excellent agreement to measured $mathrm{V}_{mathrm{ret}}$ distribution is demonstrated. The methodology validated in this work could be applied to other technology nodes as well, to get a better $mathrm{V}_{mathrm{ret}}$ yield estimation.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125477999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Fast, Accurate Leakage Power Models for IEEE P2416","authors":"Barkha Gupta, W. R. Davis","doi":"10.1109/ISQED.2019.8697565","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697565","url":null,"abstract":"Recent results in power modeling for the emerging IEEE Standard Association project P2416 are presented. The standard promises to bring accurate power-modeling capability to system-level digital design tools. This paper presents the leakage power-model characterization approach in detail in the context of a simple four-gate circuit. Simulation results with a commercial 45nm technology over a range of temperatures and supply voltages show agreement with SPICE to within 1.8% on average and 16.6% in the worst case with a speedup of over 15,000X.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform","authors":"Masoud Zabihi, Zhengyang Zhao, D. Mahendra, Z. Chowdhury, Salonik Resch, Thomas J. Peterson, Ulya R. Karpuzcu, Jianping Wang, S. Sapatnekar","doi":"10.1109/ISQED.2019.8697377","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697377","url":null,"abstract":"We present the Spin Hall Effect (SHE) Computational Random Access Memory (CRAM) for in-memory computation, incorporating considerations at the device, gate, and functional levels. For two specific applications (2-D convolution and neuromorphic digit recognition), we show that SHE-CRAM is 3x faster and has over 4x lower energy than a prior STT-based CRAM implementation, and is over 2000x faster and at least 130x more energy-efficient than state-of-the-art near-memory processing.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128446775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays","authors":"S. Amer, G. Rose","doi":"10.1109/ISQED.2019.8697361","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697361","url":null,"abstract":"This work proposes a reliable and an energy efficient Multi-Driver write scheme for 1S1R ReRAM crossbar arrays. The IR drop induced by the line resistance results in a significant degradation of the delivered voltage across the selected cell. This degradation hampers the write window and may cause write disturbance. It also increases the write latency resulting in increased energy consumption of the crossbar array. To this end, the Multi-Driver write scheme, proposed in this work, improves the voltage delivered across the selected cell via reducing the effective line resistance. This enhancement in voltage delivery improves the write margin. In addition, it allows for reducing the write voltage that reduces both write disturbance and energy consumption of the crossbar array. It is shown that for large crossbar arrays, Multi-Driver write scheme outperforms the conventional write approach while its gains are suppressed for small crossbar arrays.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128593567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards Collaborative Intelligence Friendly Architectures for Deep Learning","authors":"Amir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram","doi":"10.1109/ISQED.2019.8697647","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697647","url":null,"abstract":"Modern mobile devices are equipped with highperformance hardware resources such as graphics processing units (GPUs), making the end-side intelligent services more feasible. Even recently, specialized silicons as neural engines are being used for mobile devices. However, most mobile devices are still not capable of performing real-time inference using very deep models. Computations associated with deep models for today's intelligent applications are typically performed solely on the cloud. This cloud-only approach requires significant amounts of raw data to be uploaded to the cloud over the mobile wireless network and imposes considerable computational and communication load on the cloud server. Recent studies have shown that the latency and energy consumption of deep neural networks in mobile applications can be notably reduced by splitting the workload between the mobile device and the cloud. In this approach, referred to as collaborative intelligence, intermediate features computed on the mobile device are offloaded to the cloud instead of the raw input data of the network, reducing the size of the data needed to be sent to the cloud. In this paper, we design a new collaborative intelligence friendly architecture by introducing a unit responsible for reducing the size of the feature data needed to be offloaded to the cloud to a greater extent, where this unit is placed after a selected layer of a deep model. This unit is referred to as the butterfly unit. The butterfly unit consists of the reduction unit and the restoration unit. The outputs of the reduction unit is offloaded to the cloud server on which the computations associated with the restoration unit and the rest of the inference network are performed. Both the reduction and restoration units use a convolutional layer as their main component. The inference outcomes are sent back to the mobile device. The new network architecture, including the introduced butterfly unit after a selected layer of the underlying deep model, is trained end-to-end. Our proposed method, across different wireless networks, achieves on average 53x improvements for end-to-end latency and 68 x improvements for mobile energy consumption compared to the status quo cloud-only approach for ResNet-50, while the accuracy loss is less than 2 %.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128039819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}