20th International Symposium on Quality Electronic Design (ISQED)最新文献

Amoeba-Inspired Stochastic Hardware SAT Solver 受变形虫启发的随机硬件SAT求解器

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-04-23 DOI: 10.1109/ISQED.2019.8697729

Kazuaki Hara, N. Takeuchi, M. Aono, Yuko Hara-Azumi

引用次数: 9

Accelerating Deterministic Bit-Stream Computing with Resolution Splitting 利用分辨率分割加速确定性比特流计算

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-04-23 DOI: 10.1109/ISQED.2019.8697443

M. Najafi, S. R. Faraji, Bingzhe Li, D. Lilja, K. Bazargan

引用次数: 9

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications 低功耗和超低功耗应用中带内垫片的垂直堆叠栅极全能mosfet的速度优化

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-04-23 DOI: 10.1109/ISQED.2019.8697706

Ya-Chi Huang, M. Chiang, Shui-Jinn Wang

引用次数: 2

State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency 为提高电源效率而进行的状态保持动态DRAM库重新配置

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697347

Kaustav Goswami, H. Mondal, Shirshendu Das, D. Banerjee

引用次数: 2

Impact of Double-Row Height Standard Cells on Placement and Routing 双排高度标准单元对放置和路由的影响

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697712

Rung-Bin Lin, Yu-Xiang Chiang

引用次数: 2

MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture 非易失性存储器结构中高性能处理的Mat并行性

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697441

Joonseop Sim, Min-su Kim, Yeseong Kim, Saransh Gupta, Behnam Khaleghi, T. Simunic

{"title":"MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture","authors":"Joonseop Sim, Min-su Kim, Yeseong Kim, Saransh Gupta, Behnam Khaleghi, T. Simunic","doi":"10.1109/ISQED.2019.8697441","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697441","url":null,"abstract":"In the Internet of Things (IoT) era, data movement between processing units and memory is a critical factor in the overall system performance. Processing-in-Memory (PIM) is a promising solution to address this bandwidth bottleneck by performing a portion of computation inside the memory. Many prior studies have enabled various PIM operations on nonvolatile memory (NVM) by modifying sense amplifiers (SA). They exploit a single sense amplifier to handle multiple bitlines with a multiplexer (MUX) since a single SA circuit takes much larger area than an NVM 1-bit cell. This limits potential parallelism that the PIM techniques can ideally achieve. In this paper, we propose MAPIM, mat parallelism for high-performance processing in non-volatile memory architecture. Our design carries out multiple bit-lines (BLs) requests under a MUX in parallel with two novel design components, multi-column/row latch (MCRL) and shared SA routing (SSR). The MCRL allows the address decoder to activate multiple addresses in both column and row directions by buffering the consecutively-requested addresses. The activated bits are simultaneously sensed by the multiple SAs across a MUX based on the SSR technique. The experimental results show that MAPIM is up to $pmb{339}times$ faster and $pmb{ 221}times$ more energy efficient than a GPGPU. As compared to the state-of-the-art PIM designs, our design is $pmb{16}times$ faster and $pmb{ 1.8}times$ more energy efficient with insignificant area overhead.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A General Framework to Map Neural Networks onto Neuromorphic Processor 将神经网络映射到神经形态处理器的通用框架

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697495

Haowen Fang, Amar Shrestha, Ziyi Zhao, Yanzhi Wang, Qinru Qiu

{"title":"A General Framework to Map Neural Networks onto Neuromorphic Processor","authors":"Haowen Fang, Amar Shrestha, Ziyi Zhao, Yanzhi Wang, Qinru Qiu","doi":"10.1109/ISQED.2019.8697495","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697495","url":null,"abstract":"Bio-inspired neuromorphic hardware is an emerging computing architecture, which features highly parallel and distributed computing elements similar to the functionality of human brain. Recent study shows that neuromorphic hardware can achieve state-of-the-art performance in various cognitive tasks. However, limitations in fabrication technology has led to limitations in fan-in, fan-out, memory capacity, connectivity etc., making neuromorphic chips difficult to program. Neural networks have to satisfy specific constraints in order to be mapped to hardware, which not only requires developers to have knowledge of specific hardware, but also makes training difficult. We proposed a general framework to address above issues. It consists of a workflow to convert an existing neural network to satisfy the hardware constrains while minimizing the error caused by conversion, algorithms to increase hardware resource utilization and minimize on-chip communication cost are also proposed and evaluated. The experimental results show that the framework reduces conversion error to 0.67%, and reduces 53% of communication latency.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"109 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117311588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks 基于上下文感知的多阶段卷积神经网络能量-精度权衡

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697497

Katayoun Neshatpour, F. Behnia, H. Homayoun, Avesta Sasan

引用次数: 14

kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier kNN-CAM:基于k近邻的可配置近似浮点乘法器

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697584

Ming Yan, Yuntao Song, Yiyu Feng, G. Pasandi, Massoud Pedram, Shahin Nazarian

{"title":"kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier","authors":"Ming Yan, Yuntao Song, Yiyu Feng, G. Pasandi, Massoud Pedram, Shahin Nazarian","doi":"10.1109/ISQED.2019.8697584","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697584","url":null,"abstract":"In many real computations such as arithmetic operations in hidden layers of a neural network, some amounts of inaccuracies can be tolerated without degrading the final results (e.g., maintaining the same level of accuracy for image classification). This paper presents design of kNN-CAM, a k-Nearest Neighbors (kNN)-based Configurable Approximate floating point Multiplier. kNN-CAM utilizes approximate computing opportunities to deliver significant area and energy savings. A kNN engine is trained on a sufficiently large set of input data to learn the quantity of bit truncation that can be performed in each floating point input with the goal of minimizing energy and area. Next, this trained engine is used to predict the level of approximation for unseen data. Experimental results show that kNN-CAM provides about 67% area saving and 19% speedup while losing only 4.86% accuracy when compared to a 100% accurate multiplier. Furthermore, the application of kNN-CAM in implementation of a handwritten digit recognition provides 47.2% area saving while the accuracy is dropped by only 0.3%.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Fast Mapping-Based High-Level Synthesis of Pipelined Circuits 基于快速映射的流水线电路高级综合

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697596

Chaofan Li, S. Sapatnekar, Jiang Hu

引用次数: 0