{"title":"Impact of Double-Row Height Standard Cells on Placement and Routing","authors":"Rung-Bin Lin, Yu-Xiang Chiang","doi":"10.1109/ISQED.2019.8697712","DOIUrl":null,"url":null,"abstract":"In this article we propose a systematic method to study how increasing use of double-row height cells would impact placement and routability of a circuit. To facilitate our study, we handcraft 87 standard cells, each of which has two layouts of the same area, one designed with single-row height and the other designed with double-row height. Experimental results show that the compromise made by placement, later turned into routability degradation, for handling double-row height cells reaches its peak when a circuit has about 30% of the cells being double-row height cells if placement is done with a core utilization of 90%. It is about 40% if a core utilization of 80% is employed.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"20th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2019.8697712","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this article we propose a systematic method to study how increasing use of double-row height cells would impact placement and routability of a circuit. To facilitate our study, we handcraft 87 standard cells, each of which has two layouts of the same area, one designed with single-row height and the other designed with double-row height. Experimental results show that the compromise made by placement, later turned into routability degradation, for handling double-row height cells reaches its peak when a circuit has about 30% of the cells being double-row height cells if placement is done with a core utilization of 90%. It is about 40% if a core utilization of 80% is employed.