Accelerating Deterministic Bit-Stream Computing with Resolution Splitting

M. Najafi, S. R. Faraji, Bingzhe Li, D. Lilja, K. Bazargan
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引用次数: 9

Abstract

Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of $2^{2n}$ cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than $\pmb{2000}\times$ compared to the prior state-of-the-art deterministic bit-stream-based design.
利用分辨率分割加速确定性比特流计算
确定性的随机计算方法(SC)最近被提出,以产生完全准确的结果与随机逻辑。当期望确定的零错误率输出时,处理时间长是这些方法的主要限制。例如,当两个n位精度输入值相乘时,需要$2^{2n}$周期的处理时间。这种较长的处理时间使得当前SC的确定性方法在许多应用中效率低下。在这项工作中,我们提出了一种基于分辨率分裂的加速方法来缓解这种长延迟。其结果是处理时间的指数级减少,代价是硬件面积的一些增加。处理时间的指数减少导致能源消耗的显著减少。综合结果表明,对于常见的2输入乘法器,与先前最先进的基于确定性比特流的设计相比,所提出的设计减少了超过$ $ pmb{2000} $ $的能耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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