20th International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs 采用赛灵思fpga的DSP48E1模块的高性能noc

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697444

P. Prasad, Khyamling Parane, B. Talawar

{"title":"High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs","authors":"P. Prasad, Khyamling Parane, B. Talawar","doi":"10.1109/ISQED.2019.8697444","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697444","url":null,"abstract":"The hard multiplexers of the Xilinx DSP48E1 slices have been employed to support the functionality of crossbar switch of the buffered five port Network-on-Chip (NoC) routers. This is possible due to the dynamic mode operation of the DSP48E1 slices per clock cycle based on the multiplexer control signals. As a result of this, a significant reduction in the soft logic $(mathbf{LUT}+mathbf{FF})$ utilization of the FPGA implementation of the $6times 6$ Mesh topology has been observed. DSP based crossbar implementation of the $6times 6$ Mesh topology consumes 36% fewer LUTs and 40% fewer FFs than the LUT based crossbar implementation. 38% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 41% fewer LUTs compared to the state-of-the-art CON-NECT NoC generation tool. The latency reductions of 31% and 38% have been achieved by the proposed DSP48E1 based crossbar implementation over the LUT crossbar implementation of $8times 8$ Mesh topology under the Uniform and Transpose traffic patterns. Also, the proposed DSP48E1 based implementation achieves the saturation throughput improvements of $1.4times$ and $1.6times$ over the LUT based implementation under Uniform and Transpose traffic patterns respectively.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130616663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults 基于单故障测试模式的双卡故障测试模式自动生成

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697831

P. Wang, A. M. Gharehbaghi, M. Fujita

{"title":"Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults","authors":"P. Wang, A. M. Gharehbaghi, M. Fujita","doi":"10.1109/ISQED.2019.8697831","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697831","url":null,"abstract":"Multiple faults are more likely to occur in the fabricated circuits since they have been becoming larger and denser in the past decades. There have been researches that propose the ATPG method to deal with double faults by quickly selecting all the undetected faults by the test patterns for the single fault, and then generating the additional test patterns for those undetected faults. However, the generated test patterns may not be complete to cover all the double faults, and the test generation process cannot be completed in an acceptable runtime. In order to solve those problems, we propose an improved ATPG method which can detect all the double faults, covering all the cases overlooked by the previous research. Moreover, the execution time is significantly reduced by adequately integrating all the external tools and programs, as well as employing strategies such as circuit partitioning and bit parallel processing to accelerate the speed of fault simulation and the SAT process. To fully understand the performance of the proposed method, we comprehensively analyze the experimental results in several different aspects, which demonstrate that our method can quickly generate compact test patterns for double stuck-at faults on the circuits whose single stuck-at faults can be generated. Since the proposed method efficiently generates test patterns for the remaining double faults that cannot be detected given the test patterns for single faults, it can be inductively extended to generate test patterns for triple faults, quadruple faults, …, to cover all the multiple faults.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133350484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Small Memory Footprint Neural Network Accelerators 小内存占用神经网络加速器

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697641

Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, N. Dutt

{"title":"Small Memory Footprint Neural Network Accelerators","authors":"Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, N. Dutt","doi":"10.1109/ISQED.2019.8697641","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697641","url":null,"abstract":"Deep Neural Network (DNN) accelerators provide high-accuracy data recognition that are commonly used in edge devices. However, resource constrained edge devices usually have small form factors and limited amounts of resources, whereas DNN accelerators require large amounts of computations and memory footprint. In particular, the memory requirements of DNNs become a major bottleneck for realization of accelerators on small footprint devices. To reduce the memory footprint, fused-layer convolutional neural network (CNN) accelerators have been proposed for image recognition networks. Fused-layer CNNs reduce off-chip memory accesses by executing a set of CNN layers on-chip and by replacing the off-chip memory accesses with on-chip memory accesses between the layers. Although fused-layer CNNs reduce the off-chip memory accesses, they still require large amounts of on-chip memories that occupy significant chip area, making impractical their realization on small footprint devices. We address this problem by proposing a design technique that generates fused-CNN accelerators with small memory footprints, demonstrate its potential via a case study.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Dynamic Reconfiguration of CNNs for Input-Dependent Approximation 基于输入依赖逼近的cnn动态重构

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697843

Maedeh Hemmat, A. Davoodi

{"title":"Dynamic Reconfiguration of CNNs for Input-Dependent Approximation","authors":"Maedeh Hemmat, A. Davoodi","doi":"10.1109/ISQED.2019.8697843","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697843","url":null,"abstract":"In this work, we propose a novel framework which enables dynamic reconfiguration of an already-trained Convolutional Neural Network (CNN) in hardware during inference. The reconfiguration enables input-dependent approximation of the CNN to achieve power saving without much degradation in its classification accuracy at run-time. For each input, our framework uses only a fraction of the CNN's edge weights based on that input (with the rest remaining 0) to conduct the inference. Consequently, power saving is possible due to fewer number of fetches from off-chip memory as well as fewer multiplications for majority of the inputs. To achieve per-input approximation, we use clustering algorithm which groups similar weights in the CNN based on their importance, and design an iterative framework which decides how many clusters of weights should be fetched from off-chip memory for each individual input. We also propose new hardware structures to implement our framework on top of a recently-proposed FPGA-based CNN accelerator. In our experiments with popular CNNs, we show significant power saving with almost no degradation in classification accuracy due to doing inference with only a fraction of the edge weights for the majority of the inputs.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130424580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework 基于深度学习的晶圆图故障模式识别框架

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-06 DOI: 10.1109/ISQED.2019.8697407

Tsutomu Ishida, Izumi Nitta, D. Fukuda, Yuzi Kanazawa

引用次数: 30

An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs EDA软件测试的人工智能方法:在fpga的净延迟算法中的应用

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697652

Madhu Raman, N. Abdallah, J. Dunoyer

引用次数: 3

Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits 单片三维集成电路布线复杂度最小化

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697450

Sheng-En David Lin, D. Kim

引用次数: 0

Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems 可配置系统多目标优化设计空间子集评估

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697511

Mohamad Hammam Alsafrjalani, Tosiron Adegbija, L. Ramamoorthi

{"title":"Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems","authors":"Mohamad Hammam Alsafrjalani, Tosiron Adegbija, L. Ramamoorthi","doi":"10.1109/ISQED.2019.8697511","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697511","url":null,"abstract":"Design space subsetting has been used to select configurations that are suitable for a target design objective. However, given the growing number of design constraints and objectives (energy, performance, EDP, temperature, user expectations, etc.) selecting the best subset for a single objective may no longer satisfy current design requirements. Additionally, the increasing design space sizes in emerging systems, and the variety of configurations that can satisfy multiple objectives, makes design space subsetting very challenging. In this paper, using a configurable cache as a case study, we evaluate the impact of design space subsetting for multi-objective optimization of performance, energy, and temperature. Using a design space of 243 configurations, yielding up to 1.4 X 1073 subsets, we evaluate the quality of the subsets obtained for one design constraint against the complete design space and against the remaining design objectives (e.g., best energy subsets for performance and thermal optimization). Our results reveal that prior subsetting methods are insufficient to meet current design trends due to the correlation between design objectives. Our results also suggest that large subsets of 10 or more configurations are required to maintain multi-objective optimization results that are within 3% of the optimal.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133501542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resilient Reorder Buffer Design for Network-on-Chip 片上网络弹性重排序缓冲器设计

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697766

Zheng Xu, J. Abraham

引用次数: 0

Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs 自热对FinFET和GAAFET设计性能和可靠性的影响

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697786

Vidya A. Chhabria, S. Sapatnekar

引用次数: 9