20th International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation 适用于门级电路仿真的负偏置温度不稳定性紧凑模型

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697494

X. Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou

引用次数: 0

Deterministic Stochastic Computation Using Parallel Datapaths 基于并行数据路径的确定性随机计算

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697451

Alexander J. Groszewski, Travis Lenz

{"title":"Deterministic Stochastic Computation Using Parallel Datapaths","authors":"Alexander J. Groszewski, Travis Lenz","doi":"10.1109/ISQED.2019.8697451","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697451","url":null,"abstract":"Although one of the main appeals of Stochastic Computation is that complicated arithmetic operations can be performed with incredibly simple circuitry, it suffers from high latency due to the required bit stream length and the area incurred from generating them. Using deterministic bit streams addresses the area problem to some degree, but latency is still an issue. One of the main contributors to this high latency is the fact that each operation is performed serially, and we argue that due to the uniform nature of deterministic stochastic representations this is not necessary. Using the multiply-accumulate (MAC) operation as the target application, our research addresses this latency issue by exploiting data-level parallelism: the bottleneck of a single arithmetic unit is broken by splitting into multiple “parallel datapaths”, effectively reducing overall latency by a factor of $ at the cost of area. We demonstrate how modifying the amount of parallelism can provide a means of trading off some of these performance gains with area reduction. Furthermore, we show that this design can deliver considerable performance and energy-saving benefits for an operation that has broad applications in Machine Learning: the inner-product. Finally, we will show that this drastic reduction in computation time through parallelization can pays dividends on energy consumption per operation, with the fully parallelized MAC circuit consuming nearly 4x less energy than its serial counterpart.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128249931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

MReC: A Multilayer Photonic Reservoir Computing Architecture MReC:一种多层光子库计算架构

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697621

Dharanidhar Dhang, S. Hasnain, R. Mahapatra

引用次数: 6

VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology VeriSFQ:单通量量子技术的半形式化验证框架和基准

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697701

A. D. Wong, Kevin Su, Hang Sun, A. Fayyazi, Massoud Pedram, Shahin Nazarian

{"title":"VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology","authors":"A. D. Wong, Kevin Su, Hang Sun, A. Fayyazi, Massoud Pedram, Shahin Nazarian","doi":"10.1109/ISQED.2019.8697701","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697701","url":null,"abstract":"In this paper, we propose a semi-formal verification framework for single-flux quantum (SFQ) circuits called VeriSFQ, using the Universal Verification Methodology (UVM) standard. The considered SFQ technology is superconducting digital electronic devices that operate at cryogenic temperatures with active circuit elements called the Josephson junction, which operate at high switching speeds and low switching energy - allowing SFQ circuits to operate at frequencies over 300 gigahertz. Due to key differences between SFQ and CMOS logic, verification techniques for the former are not as advanced as the latter. Thus, it is crucial to develop efficient verification techniques as the complexity of SFQ circuits scales. The VeriSFQ framework focuses on verifying the key circuit and gate-level properties of $mathrm{SFQ}$ logic: fanout, gate-level pipeline, path balancing, and input-to-output latency. The combinational circuits considered in analyzing the performance of VeriSFQ are: Kogge-Stone adders (KSA), array multipliers, integer dividers, and select ISCAS’85 combinational benchmark circuits. Methods of introducing bugs into SFQ circuit designs for verification detection were experimented with - including stuck-at faults, fanout errors, unbalanced paths, and functional bugs like incorrect logic gates. In addition, we propose an SFQ verification benchmark consisting of combinational SFQ circuits that exemplify SFQ logic properties and present the performance of the VeriSFQ framework on these benchmark circuits. The portability and reusability of the UVM standard allows the VeriSFQ framework to serve as a foundation for future SFQ semi-formal verification techniques.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing 考虑分布式/并行计算通信结构的算法综合

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697224

Yukio Miyasaka, A. Mittal, M. Fujita

{"title":"Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing","authors":"Yukio Miyasaka, A. Mittal, M. Fujita","doi":"10.1109/ISQED.2019.8697224","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697224","url":null,"abstract":"There are increasing opportunities to calculate with distributed/parallel computing: many-core CPU, GPU, and FPGA. It is, however, generally difficult to come up with an algorithm suitable for distributed/parallel computing. There have been many researches on the automatic partitioning of programs and designs, but they have not performed reconstruction of the data flow in the algorithm level. In this paper, we apply partial synthesis method and synthesize algorithms for distributed/parallel environment automatically. We propose the template-based computing that aims to prevent the communications among the cores and chips to become overhead. With that template, an algorithm is synthesized by using conventional partial synthesis method, which performs synthesis iteratively modifying the template. The synthesis-problem generally becomes infeasible as its size becomes larger. Therefore, we propose the method to reduce the search space by adding constraints. The synthesis is performed for small instances of the target problem at first, and then the additional constraints are considered based on the synthesized algorithm. In the experiment, we synthesized algorithms for matrix vector multiplication with one-way-ring-connected nodes to matrix of $32times 32$.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130326762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

On SAT-Based Attacks On Encrypted Sequential Logic Circuits 基于sat的加密顺序逻辑电路攻击研究

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697421

Yasaswy Kasarabada, Suyuan Chen, R. Vemuri

引用次数: 18

Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits 泄漏优势电路合成的驱动强度选择

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697877

Mahfuzul Islam, S. Nishizawa, Yasuhiro Matsui, Yoshinobu Ichida

引用次数: 2

PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications PUF- passse:用于物联网应用的基于PUF的密码强度增强器

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697540

Qian Wang, Mingze Gao, G. Qu

引用次数: 3

Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools 估计帕累托最优前沿，以确定电子设计自动化工具中的旋钮设置

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/ISQED.2019.8697576

Bill Huggins, W. R. Davis, P. Franzon

{"title":"Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools","authors":"Bill Huggins, W. R. Davis, P. Franzon","doi":"10.1109/ISQED.2019.8697576","DOIUrl":"https://doi.org/10.1109/ISQED.2019.8697576","url":null,"abstract":"The ability to configure physical design tools is often dependent on the experience and knowledge of the physical designer (PD). Technology node sizes are ever decreasing, digital design sizes vary drastically, and design constraints change based on the needs of the application. As these changes occur frequently and physical design times can be extensive, the need for accurate quality of design results early in the design process is crucial. Collecting these metrics is computationally expensive, creating a need to determine how to best create and extract information as design flows change. This paper describes the use of estimated Pareto optimal trade-off sets to provide designers with the capability of visualizing the results of Electronic Design Automation (EDA) tool configuration settings, or “knobs”, that will offer an optimal post detail route design based on two design metrics, critical path length and core area. We will show that when given a set of design constraints by creating a point that occurs along the Pareto front, the knob settings used are optimal. With only 38 samples per design, we were able to produce estimated detail routed design metrics with a worst case error (WCE) of less than 10%.","PeriodicalId":128327,"journal":{"name":"20th International Symposium on Quality Electronic Design (ISQED)","volume":"555 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123932956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

General Information 一般信息

20th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-03-01 DOI: 10.1109/isqed.2019.8697427

引用次数: 0