Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits

Abstract

For a highly duty-cycled IoT device, the circuit spends most of the time in sleep mode. As a result, leakage-energy becomes the dominant energy consumption source. Therefore, circuit design to minimize the leakage-power has become a critical issue. The state-of-the-art standard-cell library is optimized for high-performance designs and is power-hungry. We show that choosing a suitable set of drive-strengths can reduce the leakage-energy by order magnitudes for highly duty-cycled devices. To realize the suitable set, cells with larger gate-lengths or stacked devices are essential although they increase cell area and gate capacitance. The holistic property of a standard-cell library ensures that a better circuit can be synthesized with the slow cells in the library. We have compared two libraries with one being “thin & dense” in its drive-strength varieties, while the other being fat and sparse. Synthesis results using ISCAS‘85 circuits show a maximum of 1/5 reduction of leakage-power with our proposed “fat & sparse” library than that with a conventional “thin & dense” library.