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2016 5th International Symposium on Next-Generation Electronics (ISNE)最新文献

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Decoding of QR codes printed on spheres 解码打印在球体上的二维码
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543336
K. Lay, Lee-Jyi Wang, Pei-Lun Han
{"title":"Decoding of QR codes printed on spheres","authors":"K. Lay, Lee-Jyi Wang, Pei-Lun Han","doi":"10.1109/ISNE.2016.7543336","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543336","url":null,"abstract":"In this paper, we deal with the situation wherein QR codes are printed on spheres. When an image is obtained from such a QR code, it can be seriously distorted. A scheme based on conic segmentation (CS) is proposed to rectify the distorted QR images.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128507060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate 建立了工作于亚阈值逻辑门的无结双栅极场效应管(JLDGFET)的噪声裕度和平均静态功率模型
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543300
T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang
{"title":"A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate","authors":"T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang","doi":"10.1109/ISNE.2016.7543300","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543300","url":null,"abstract":"Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131501939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design a test chip to find out mixed signal interference with broad range instrumentation amplifier 设计了一种检测宽量程仪表放大器混合信号干扰的测试芯片
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543366
Neeraj Agarwal, Neeru Agarwal, Manisha Sharma
{"title":"Design a test chip to find out mixed signal interference with broad range instrumentation amplifier","authors":"Neeraj Agarwal, Neeru Agarwal, Manisha Sharma","doi":"10.1109/ISNE.2016.7543366","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543366","url":null,"abstract":"In this Paper, issues related to substrate coupling in system on chip design are described and demonstrated including the physical phenomenon responsible for its creation, coupling transmission mechanism and media, parameter affecting coupling strengths and its impact on mixed signal integrated circuits. A test chip to find out various aspect of mixed signal interference is planned in 0.8pm N well P sub CMOS technology 5V double poly double metal process. Basic aim of chip is to find out magnitude of interference happening when analog and digital circuit is placed nearby on a common substrate. An instrumentation amplifier with high CMRR is also designed for noise sensing. MOSFET capacitors at the input of instrumentation amplifier are used for the picking of substrate interference.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A numerical investigation on effects of lateral Si/SiO2 interface traps on magnetic sensitivity of sectorial SD-MAGFET 横向Si/SiO2界面陷阱对扇形SD-MAGFET磁灵敏度影响的数值研究
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543340
Zhenyi Yang, C. Leung, P. Lai, P. Pong
{"title":"A numerical investigation on effects of lateral Si/SiO2 interface traps on magnetic sensitivity of sectorial SD-MAGFET","authors":"Zhenyi Yang, C. Leung, P. Lai, P. Pong","doi":"10.1109/ISNE.2016.7543340","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543340","url":null,"abstract":"This work studies the influence of the Si/SiO2 interface traps at the sidewall of sectorial SD-MAGFET in detail. Ionized acceptor traps work like negative oxide charges to enhance the magnetic sensing of the device by depleting the conduction channel, but ionized donor traps behave like positive oxide charges to weaken the magnetic sensing by inducing a parasitic channel at the sidewall. In particular, the higher the density of the acceptor or donor traps, the stronger is the effect on the magnetic sensitivity. Moreover, the trap energy also affects the sensitivity, with larger effect for traps lying closer to the valence or conduction band.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127367469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A panoramic stitching vision performance improvement technique for Minimally Invasive Surgery 一种用于微创手术的全景拼接视力改善技术
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543381
D. Kim, Ching-Hwa Cheng
{"title":"A panoramic stitching vision performance improvement technique for Minimally Invasive Surgery","authors":"D. Kim, Ching-Hwa Cheng","doi":"10.1109/ISNE.2016.7543381","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543381","url":null,"abstract":"Minimally Invasive Surgery (MIS) is a current prevalent technique for surgical operations. Compared with traditional surgical methods, MIS can reduce the post-surgical recovery time, as well as the costs and pain patients endure as a result of surgery. It is therefore of interest to both doctors and patients. The major problem of MIS is there being a narrow field of vision. We have developed and validated a MIS Panoramic Endoscope (MISPE) [4] to provide doctors with broad fields of view. MISPE features a combination of image overlapping and image stitching. The panoramic image apparatus has two side-by-side endoscopic lenses that provide wide-angle inputs for image stitching. MISPE can provide doctors with panoramic images, so that doctors can easily discriminate the organ's positions between surgical operations. The two issues of concern of MISPE are the quality and speed of image stitching. However, the image stitching results of MISPE cannot be obtained by using the conventional SIFT[1], SURF[2], or ORB[3] algorithms. Therefore, this paper proposes few novel techniques to improve the image stitching performance of MISPE. Experimental results show that MISPE can enhance the image size by up to 150%. We also obtained 2X performance improvement in comparison with the conventional techniques.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134368936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Flipped voltage follower ISFET readout circuits 翻转电压跟随器ISFET读出电路
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543382
Surachoke Thanapitak, C. Sawigun
{"title":"Flipped voltage follower ISFET readout circuits","authors":"Surachoke Thanapitak, C. Sawigun","doi":"10.1109/ISNE.2016.7543382","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543382","url":null,"abstract":"ISFET readout circuits based on the flipped voltage follower is proposed. The circuits operate at 0.8 V providing an ability to sense pH linearly from 1 to 13 with 44.5mV/pH sensitivity. In comparison with relevant literature, the proposed circuits are the most power-efficient.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134448779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3D memory design based on through silicon vias enabled timing optimization 基于硅通孔使能定时优化的三维存储器设计
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543367
Xiaowei Chen, Seyed Alireza Pourbakhsh, L. Hou, Na Gong, Jinhui Wang
{"title":"3D memory design based on through silicon vias enabled timing optimization","authors":"Xiaowei Chen, Seyed Alireza Pourbakhsh, L. Hou, Na Gong, Jinhui Wang","doi":"10.1109/ISNE.2016.7543367","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543367","url":null,"abstract":"In three-dimensional (3D) integrated circuit (IC), a large number of dummy through silicon vias (TSV) are required for thermal and thinning concerns. However, limited attention is paid to the fact that these dummy TSVs can be multi-functional and used for timing purposes. In this paper, we propose to use those \"timing wasteful\" dummy TSVs to replace bit line delay cells. Also, a TSV allocation algorithm is presented to optimize the TSV array layout. Finally, three memory designs are implemented to verify the feasibility and reliability of the proposed technology. It is found that all delay cells in these 3 memories can be replaced by TSV arrays.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"16 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133203953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Three-phase filtered SVPWM motor drive 三相滤波SVPWM电机驱动
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543400
Keng-Yuan Chen, M. Peng, Chyi-Sheng Huang
{"title":"Three-phase filtered SVPWM motor drive","authors":"Keng-Yuan Chen, M. Peng, Chyi-Sheng Huang","doi":"10.1109/ISNE.2016.7543400","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543400","url":null,"abstract":"In the digital implementation, PWM pulses can only change switching states at some specific time instants depending on the system clock frequency. This phenomenon results in the deviation between the desired and the produced phase voltages. Although the deviation is small in each carrier period, the accumulated error will result in large current harmonics for inductive load. In this paper, a high-order filtered SVPWM is proposed for the three-phase motor drive to overcome this problem. By further incorporating the band-stop filter, the specific harmonic component is reduced. Two experiments confirm the reliability and applicability of the proposed modulator.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121276763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF-powered battery-less Wireless Sensor Network 射频供电无电池无线传感器网络
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543351
Ruisi Ge, Hong Pan, Zhibin Lin, L. Hou, Na Gong, Jinhui Wang
{"title":"RF-powered battery-less Wireless Sensor Network","authors":"Ruisi Ge, Hong Pan, Zhibin Lin, L. Hou, Na Gong, Jinhui Wang","doi":"10.1109/ISNE.2016.7543351","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543351","url":null,"abstract":"Wireless Sensor Networks (WSNs) have attracted more attentions due to its low cost and convenience. Despite the great potential, power supply restricts the application of WSNs. Especially in the environment such as rural areas, underground and underwater structures, the electrical wire or battery increases the cost of installation and brings the unexpected inconvenience. In this abstract, a far-field radio frequency (RF) powered wireless sensor network is presented. Moreover, a mesh network approach is proposed to solve the data collision issue caused by the discontinuous power supply. Test results verify the feasibility and reliability of this WSNs.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121480263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low noise class-C voltage-controlled oscillator with left-handed resonator 一种低噪声c类压控振荡器，带有左旋谐振腔
2016 5th International Symposium on Next-Generation Electronics (ISNE) Pub Date : 2016-05-04 DOI: 10.1109/ISNE.2016.7543352
S. Jang, W. Lai, Tsui-Chun Kung
{"title":"A low noise class-C voltage-controlled oscillator with left-handed resonator","authors":"S. Jang, W. Lai, Tsui-Chun Kung","doi":"10.1109/ISNE.2016.7543352","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543352","url":null,"abstract":"This letter proposes a low phase noise CMOS voltage-controlled oscillator (VCO) using a left-handed (LH) LC network and a switching/tuning varactor pair. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the die area of the oscillator is 0.527 × 0.749 mm2. The VCO can generate differential signals in the high (low)-band frequency range of 6.042~6.163(4.038~4.225) GHz. The measured high (low)-band figure of merit (FOM) is -190.2 (-188.6)dBc/Hz.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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