T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang
{"title":"建立了工作于亚阈值逻辑门的无结双栅极场效应管(JLDGFET)的噪声裕度和平均静态功率模型","authors":"T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang","doi":"10.1109/ISNE.2016.7543300","DOIUrl":null,"url":null,"abstract":"Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate\",\"authors\":\"T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang\",\"doi\":\"10.1109/ISNE.2016.7543300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.\",\"PeriodicalId\":127324,\"journal\":{\"name\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2016.7543300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate
Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.