Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)最新文献

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An accurate determination of the characteristic impedance of lossy lines on chips based on high frequency S-parameter measurements 基于高频s参数测量的芯片上损耗线特性阻抗的精确测定
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510793
Thomas-Michael Winkel, L. S. Dutta, Hartmut Grabinski
{"title":"An accurate determination of the characteristic impedance of lossy lines on chips based on high frequency S-parameter measurements","authors":"Thomas-Michael Winkel, L. S. Dutta, Hartmut Grabinski","doi":"10.1109/MCMC.1996.510793","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510793","url":null,"abstract":"A very accurate, novel determination of the characteristic impedance of interconnects on semiconducting substrates has been developed. The method is based upon high frequency, S-parameter measurements of two transmission lines of different lengths. The influence of the contact structures of the measurement probes are taken into account with the help of three additional measurements. The mathematical background of the method is presented. A comparison of the results obtained from measurements and from calculations is given and shows an excellent agreement.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116762287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Chip and package co-design technique for clock networks 时钟网络的芯片与封装协同设计技术
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510788
Qing K. Zhu, W. Dai
{"title":"Chip and package co-design technique for clock networks","authors":"Qing K. Zhu, W. Dai","doi":"10.1109/MCMC.1996.510788","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510788","url":null,"abstract":"This paper presents the motivation and a case study for a new clock distribution technique: route the global clock on package. This technique can be used in single chips and multichip modules based on area I/Os of the flip chip technology. Due to 2-4 order lower interconnect resistance on package layers, the clock skew and path delay of the clock network are significantly reduced.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies 损耗传输线拓扑互连优化中基于灵敏度的布线方法
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510780
T. Xue, E. Kuh, Qingjian Yu
{"title":"A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies","authors":"T. Xue, E. Kuh, Qingjian Yu","doi":"10.1109/MCMC.1996.510780","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510780","url":null,"abstract":"This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the maximum rising delay by over 60% with small penalty in routing area. Besides delay optimization, the final solution eliminates the over-shoot of response waveform and is robust under parameter variations.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131571126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Space-cube: a flexible computer architecture based on stacked modules 空间立方体:一种基于堆叠模块的灵活计算机体系结构
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510763
G. Bolotin
{"title":"Space-cube: a flexible computer architecture based on stacked modules","authors":"G. Bolotin","doi":"10.1109/MCMC.1996.510763","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510763","url":null,"abstract":"This paper presents a flexible, computer architecture based on stacked interchangeable modules. The architecture is ideally suited to implementation using stacked multichip modules (MCMs). The architecture, by making use of all sides of a module stack, allows simple, single bussed modules, together with a gate-way module, to be easily configured into a variety of more complicated architectures.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Development of a DSP/MCM subsystem assessing low-volume, low-cost MCM prototyping for universities 开发DSP/MCM子系统,为大学评估小批量、低成本的MCM原型
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510775
P. Dehkordi, T. Powell, D. Bouldin
{"title":"Development of a DSP/MCM subsystem assessing low-volume, low-cost MCM prototyping for universities","authors":"P. Dehkordi, T. Powell, D. Bouldin","doi":"10.1109/MCMC.1996.510775","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510775","url":null,"abstract":"This paper discusses the design and development of a general-purpose programmable DSP subsystem packaged in a multichip module. The subsystem contains a 32-bit floating-point programmable DSP processor along with 256 K-byte of SRAM; 128 K-byte of FLASH memory, 10 K-gate FPGA and a 6-channel 12-bit ADC. The complete subsystem is interconnected on a 37 mm by 37 mm MCM-D substrate and packaged in a 320-pin ceramic quad flat pack. The design has been submitted to the MIDAS brokerage service to be fabricated by Micro Module Systems. Our experience shows that low-volume MCM prototyping is achievable and somewhat affordable for universities. The design flow electrical and thermal analyses, CAD tools, cost and lessons learned are discussed in this paper.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Efficient gate delay modeling for large interconnect loads 大型互连负载的有效门延迟建模
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510795
A. Kahng, S. Muddu
{"title":"Efficient gate delay modeling for large interconnect loads","authors":"A. Kahng, S. Muddu","doi":"10.1109/MCMC.1996.510795","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510795","url":null,"abstract":"With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new /spl Pi/ model for distributed RC and RLC interconnects to estimate the driving point admittance at the output of a CMOS gate. Using this model we are able to compute the gate delay efficiently, within 25% of SPICE-computed delays. Our parameters depend only on total interconnect tree resistance and capacitance at the output of the gate, Previous \"effective load capacitance\" methods, applicable only for distributed RC interconnects, are based on /spl Pi/ model parameters obtained via a recursive admittance moment computation. Our model should be useful for iterative optimization of performance-driven routing or for estimation of gate delay and rise times in high-level synthesis.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127160639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Flexible access to MCM technology via the multichip module designers' access service (MIDAS) 通过多芯片模块设计人员访问服务(MIDAS)灵活访问MCM技术
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510774
J. Peltier, W. Hansford
{"title":"Flexible access to MCM technology via the multichip module designers' access service (MIDAS)","authors":"J. Peltier, W. Hansford","doi":"10.1109/MCMC.1996.510774","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510774","url":null,"abstract":"The MCM Designers' Access Service (MIDAS) allows designers to obtain prototype and small quantities of MCMs. The service currently maintains relationships with several MCM-D foundries, including: nChip in San Jose, CA; Micromodule Systems (MMS) in Cupertino, CA; and IBM Microelectrons in Hopewell Junction, NY. MIDAS provides a low-cost service achieved through a multi-project environment where the customers share tooling and substrate manufacturing costs. The service offers design support, distributes foundry design kits, groups the projects onto regularly scheduled runs, places orders, and supplies fully assembled modules. As well, MIDAS offers a limited selection of open-tooled, second-level packages, bare tested die (KGD), and test sockets. MIDAS functions as a technology enabler by supplying the designer with an interface \"transparent\" to the fabricator and common to multiple vendors. Foundries prefer to work with a single source who coordinates the details of user interactions. Thus, they avoid dealing with multiple customers and spare valuable overhead. The service operates on an on-going basis and has delivered modules to customers from each foundry. Commercial, military and educational/research institutions utilize the service. This paper discusses the background and current status of MIDAS. Additionally, plans for accessing mixed signal MCM technologies and flip chip bumping and assembly are reviewed.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Mixed signal digital sub-band tuner multichip module 混合信号数字子带调谐器多芯片模块
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510768
K. Sienski, C. Field, C. Schreiner, M. Chivers
{"title":"Mixed signal digital sub-band tuner multichip module","authors":"K. Sienski, C. Field, C. Schreiner, M. Chivers","doi":"10.1109/MCMC.1996.510768","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510768","url":null,"abstract":"Mixed signal designs consisting of analog and digital components bridge the gap between the sensor and data processor in a broad range of systems. As digital MCM technology matures, it becomes feasible to consider incorporating more of a system on a single substrate. In many cases, the opportunity for expansion lies in the analog and digital conversion circuitry. This paper describes the development of a mixed signal module that integrates an A/D converter and digital sub-band tuner in a single MCM. Physical isolation structures are developed to shield the analog signals from electromagnetic noise generated by the digital circuitry. A laser customized rapid prototyping technique is used to implement the design on an MCM-D substrate.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114378748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced interconnected mesh power system (IMPS) MCM topologies 先进的互联网格电力系统(IMPS) MCM拓扑
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510781
J. Parkerson, L. Schaper
{"title":"Advanced interconnected mesh power system (IMPS) MCM topologies","authors":"J. Parkerson, L. Schaper","doi":"10.1109/MCMC.1996.510781","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510781","url":null,"abstract":"A design implementation package for the automation of advanced IMP MCM topologies has been developed. The IMPS topology is a patented development of the University of Arkansas which allows a complete MCM with low impedance power distribution and dense signal interconnect, to be built on only two metal layers. The IMPS topology consists of a large number of interwoven power distribution lines. The large volume of layout structures in the IMPS topology, requires the assistance of a computer-aided design package. This paper describes advanced IMPS topologies and how the IMPS design package, along with Mentor Graphics MCM Design Station, implement the different types of meshes. An example design is used to illustrate the use of the methodology. The advanced IMPS topologies described include the nonuniform IMPS mesh, which allows for higher signal interconnect density at congested locations; the partitioned IMPS mesh, which allows for different mesh structures at different locations in the same design and the asymmetric IMPS mesh, which allows for variations in power supply impedances.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast parameters extraction of multilayer and multiconductor interconnects using geometry independent measured equation of invariance 利用几何无关不变性测量方程快速提取多层和多导体互连参数
Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI: 10.1109/MCMC.1996.510778
W. Hong, W. Sun, W. Wei-Ming Dai
{"title":"Fast parameters extraction of multilayer and multiconductor interconnects using geometry independent measured equation of invariance","authors":"W. Hong, W. Sun, W. Wei-Ming Dai","doi":"10.1109/MCMC.1996.510778","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510778","url":null,"abstract":"Measured Equation of Invariance (MEI) is a new concept in computational electromagnetics. It has been demonstrated that the MEI is such an efficient boundary truncation technique that the meshes can be terminated very close to the object and still strictly preserves the sparsity of the FD equations. Therefore, the final system matrix encountered by MEI is a sparse matrix with size similar to that of integral equation methods. However, complicated Green's function and disagreeable Sommerfeld integrals make the traditional MEI very difficult, if not impossible, to be applied to analyze multilayer and multiconductor interconnects. In this paper, we propose the Geometry Independent MEI (GIMEI) which substantially improved the original MEI method. We use GIMEI for capacitance extraction of general two-dimension VLSI multilayer and multiconductor interconnect. Numerical results are in good agreement with various published data. We also include a simple three-dimensional example and compared GIMEI with FASTCAP from MIT. The accuracy is maintained while GIMEI care generally an order of magnitude faster than FASTCAP with much less memory usage.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125770214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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