时钟网络的芯片与封装协同设计技术

Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893) Pub Date : 1996-02-06 DOI:10.1109/MCMC.1996.510788

Qing K. Zhu, W. Dai

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引用次数: 8

摘要

本文介绍了一种新的时钟分配技术——包上路由全局时钟的原理和应用实例。该技术可用于基于区域I/ o的倒装芯片技术的单芯片和多芯片模块。由于封装层的互连电阻降低了2-4个数量级，时钟网络的时钟偏差和路径延迟显著降低。

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Chip and package co-design technique for clock networks

This paper presents the motivation and a case study for a new clock distribution technique: route the global clock on package. This technique can be used in single chips and multichip modules based on area I/Os of the flip chip technology. Due to 2-4 order lower interconnect resistance on package layers, the clock skew and path delay of the clock network are significantly reduced.

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Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)

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